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publication# 15535 rev. b amendment /0 issue date: november 1993 this document contains information on a product under development at advanced micro devices, inc. the information is intended to help you to evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. 3-3 advanced micro devices AM79C864A physical layer controller with scrambler (plc-s) preliminary distinctive characteristics n implements fddi phy layer protocol for iso standard (fddi) 9314-1 n implements ansi standard stream cipher scrambling/descrambling n hardware physical connection management (pcm) support n performs physical connection insertion and removal n on-chip link error monitor (lem) and link confidence test (lct) n line state detection n repeat filter n elasticity buffer and smoother functions n 4b/5b encoding/decoding n full duplex operation n data framing n built-in self test general description the physical layer controller with scrambler (plc-s) is a cmos device which along with physical data transmitter (pdt) and physical data receiver (pdr) implements the physical layer protocol (phy) and por- tions of the station management (smt) of the ansi fi- ber distributed data interface (fddi) standard. the plc-s, pdt and pdr are collectively known as the amphy. phy functions performed by the plc-s in- clude framing of data on symbol pair boundaries, the elasticity buffer function, the smoothing function, 4b/5b encoding and decoding of symbols, line state detection, the repeat filter function, and stream cipher scram- bling/descrambling. smt functions performed include physical connection management (pcm), physical connection insertion and removal and link error monitor. the plc-s chip receives symbol-wide (5 bits) data along with a 25 mhz recovered clock from the pdr chip and searches for a jk symbol pair (also known as start- ing delimiter). it uses the starting delimiter to establish byte boundaries (i.e. to frame the data). framed data is then sent to the elasticity buffer which serves to compensate for the frequency difference be- tween the recovered clock and the local clock. data out- put by the elasticity buffer is checked by the smoother and when necessary, idle symbols are inserted be- tween frames to maintain a minimum number of idle symbols in the interframe gap. the data is then decoded and sent to the media access control (mac) chip. the data is byte-wide (10 bits) and is clocked by a 12.5 mhz local clock. the plc-s receives byte-wide data from the mac at 12.5 million bytes per second, encodes the data and sends out symbol-wide data at 25 million symbols per second to pdt chip. in the transmit path, there is a re- peat filter to detect corrupted symbols and convert them into the specified pattern of halt and idle symbols. the repeat filter in each plc-s chip converts the last byte of a frame fragment into idle symbols and thus eventually removing fragments from the ring. the plc-s device includes a stream cipher scrambler/ descrambler as prescribed in the ansi tp-pmd stan- dard for transmission over twisted-pair cable. for copper-based designs, the scrambler/descrambler may be enabled either through software or hardware. for fi- ber-based designs, the scrambler/descrambler is dis- abled by default. for a detailed description of the ansi-compliant copper fddi system using the plc-s device, refer to amd pid #18258a, implementing fddi over copper; the ansi x3t9.5 standard . the pcm initializes the connection of neighboring phys and manages the phy signaling. pcm consists of the pcm state machine, which determines the timing and state requirements for pcm, and the pcm pseudo code, which provides the information to be communi- cated to the neighboring pcm and specifies the connec- tion policies. the plc-s chip contains the pcm state machine, while the pcm pseudo code is controlled by software. the pcm state machine communicates with other pcms using a bit signaling mechanism whereby certain line states are received and transmitted. the pcm also makes use of the link error monitor in the
amd p r e l i m i n a r y 3-4 the supernet 2 family for fddi 1994 data book plc-s chip during link confidence test and after the link has been formed, to detect a noisy link. the plc-s contains a line state machine for detecting received line states and a data stream generator for transmitting the various line states. the plc-s also contains a state machine called physical connection insertion (pci) which is used in physical connection insertion and re- moval. it performs the necessary ring scrubbing and data path switching. the node processor interface in the plc-s consists of several control and status registers. the plc-s also contains error and special event counters, built in self test (bist) logic, boundary scan logic, and several data loopback multiplexers so that internal data paths may be reconfigured for test purposes. plc-s block diagram plc-s core stream cipher scrambler stream cipher descrambler tx 9C0 txpar npaddr 4-0 np 15-0 rx 9C0 rxpar tdat 4C0 control signals rdat 4C0 rsclk scrm programmable fotoff control fotoff sdo see next page for the plc-s core block diagram (optional) signal_detect control 15535b-1 lsclk itdat irdat cipher_ loopback mux
amd p r e l i m i n a r y 3-5 AM79C864A plc-s core block diagram 15535b-2 11 5 5 irdat framer elasticity buffer/ smoother bypass mux scrub mux lm local lbmux eb local lbmux receive data output receive data input error counters and timers line state machine 16 5 npaddr np control signals pcm np interface idles misc status and control 11 rx repeat filter built-in self test data stream generator encoder test data mux transmit data output remote loopback mux transmit data input tx itdat decoder
amd p r e l i m i n a r y 3-6 the supernet 2 family for fddi 1994 data book table of contents distinctive characteristics 3-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general description 3-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . plc-s block diagram 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . plc-s core block diagram 3-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table of contents 3-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . connection diagram 3-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin designations 3-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic symbol 3-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 3-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin description 3-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional description 3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . node processor interface 3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . read cycle 3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . write cycle 3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . registers 3-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . plc-s control and status registers 3-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical connection management timers 3-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical connection management timing parameters 3-28 . . . . . . . . . . . . . . . . . . . . . . physical connection management bit signaling registers 3-28 . . . . . . . . . . . . . . . . . . . event counters 3-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupt registers 3-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . built in self test register 3-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . framer 3-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . elasticity buffer 3-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . smoother operation 3-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . line state machine (lsm) 3-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . link error monitor 3-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical connection management (pcm) 3-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcm operation 3-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcm state machine 3-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pseudo code bit signaling 3-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci operation 3-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci state machine 3-38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amd p r e l i m i n a r y 3-7 AM79C864A table of contents decoder 3-39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . encoder 3-40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . scrambler 3-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . descrambler 3-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . repeat filter 3-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data stream generator 3-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data path muxes 3-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eb local loopback mux 3-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cipher loopback mux 3-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lm local loopback mux 3-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bypass mux 3-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . remote loopback mux 3-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . scrub mux 3-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . test data mux 3-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data input/output 3-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive data input 3-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive data output 3-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit data input 3-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit data output 3-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . built in self test (bist) 3-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bist operation 3-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . counter segmentation test mode 3-45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . boundary scan test mode 3-45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 3-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ranges 3-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc characteristics 3-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capacitance 3-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching characteristics 3-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching waveforms 3-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching test circuit 3-52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching test waveforms 3-53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amd p r e l i m i n a r y 3-8 the supernet 2 family for fddi 1994 data book connection diagram 120-pin pqr (top view) 15535b-3 28 29 30 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 v ss ebferr test2 test1 test0 scano v dd v ss v ss v ss scrm v ss npclk bclk v dd v ss lsclk v ss v ss ptsto encoff lsr2 v dd v ss lsr1 lsr0 v ss ulsb v ss 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 90 89 88 v dd tx1 tx2 tx3 v ss v dd tx4 tx5 tx6 tx7 tx8 tx9 v ss v dd rx9 rx8 rx7 rx6 rx5 rx4 v ss v dd rx3 rx2 rx1 rx0 rxpar v ss v dd txpar tx0 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 120 100 99 98 97 96 95 94 93 92 91 cs nprw np15 np14 np13 v ss v dd np12 np11 np10 np9 v ss v ss v ss v dd np8 np7 np6 np5 v dd np4 np3 v ss v dd np2 np1 np0 rst v ss v ss rdat0 sdo v dd npaddr3 npaddr2 npaddr1 v dd v ss npaddr0 tdat0 tdat1 tdat2 tdat3 tdat4 v dd v ss lpbck fotoff rrsclk rsclk rdat4 rdat3 v dd v ss rdat2 rdat1 v ss v ss int npaddr4
amd p r e l i m i n a r y 3-9 AM79C864A pqfp pin designations listed by pin number pin name v ss int npaddr4 npaddr3 npaddr2 npaddr1 v dd v ss npaddr0 tdat0 tdat1 tdat2 tdat3 tdat4 v dd v ss lpbck fotoff rrsclk rsclk rdat4 rdat3 v dd v ss rdat2 rdat1 v ss rdat0 sdo v dd pin number 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 pin number 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 pin number 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pin name v ss ebferr test2 test1 test0 scano v dd v ss v ss v ss scrm v ss npclk bclk v dd v ss lsclk v ss v ss ptsto encoff lsr2 v dd v ss lsr1 lsr0 v ss ulsb v ss v dd pin name v ss rxpar rx0 rx1 rx2 rx3 v dd v ss rx4 rx5 rx6 rx7 rx8 rx9 v dd v ss tx9 tx8 tx7 tx6 tx5 tx4 v dd v ss tx3 tx2 tx1 tx0 txpar v dd pin name v ss v ss rst np0 np1 np2 v dd v ss np3 np4 np5 np6 np7 np8 v dd v ss v ss v ss np9 np10 np11 np12 v dd v ss np13 np14 np15 nprw cs v dd
amd p r e l i m i n a r y 3-10 the supernet 2 family for fddi 1994 data book logic symbol rst clocks receive data transmit data power & ground control & status test pdt & pdr interface node processor interface sdo test 2C0 rrsclk encoff v dd v ss bclk npclk rsclk lsclk rdat 4C0 tx 9C0 txpar nprw npaddr 4C0 rx 9C0 rxpar np 15C0 tdat 4C0 fotoff lpbck scano ptsto ebferr ulsb lsr 2C0 cs int 15535b-4 scrm
amd p r e l i m i n a r y 3-11 AM79C864A ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: temperature range c = commercial (0 c to +70 c) package type k = 120-plastic quad flatpack in tapepak (pqr120) not applicable device number/description AM79C864A physical layer controller with scrambler (plc-s) AM79C864A AM79C864A k c valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the lo- cal amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. kc, kc\w valid combinations alternate packaging option \w = trimmed and formed in a tray (pqj120) \w
amd p r e l i m i n a r y 3-12 the supernet 2 family for fddi 1994 data book pin description clock signals bclk byte clock (input) bclk is a 12.5 mhz clock. it is used by the plc-s to clock most internal operations, clock rx 9C0 to the mac device and, along with lsclk, latch tx 9C0 from the mac device. npclk node processor clock (input) npclk is used to latch node processor inputs, run the node processor interface state machine, and clock out- put signals to the node processor. it is distinct from the bclk for test and diagnostic purposes only. for normal operations, the bclk and npclk pins must be tied together. rsclk recovered symbol clock (input) rsclk is a 25 mhz clock. it is recovered from the data sent to the physical data receiver (pdr) by the up- stream station in the ring. it is used to latch rdat 4C0 from the pdr device. it is also used for clocking the framer and the elasticity buffer input controller. lsclk local symbol clock (input) lsclk is a 25 mhz clock. it is used by the plc-s to clock tdat 4C0 to the physical data transmitter (pdt) and, along with bclk, to latch tx 9C0 from the mac device. receive data signals rx 9C0 receive data bus (output) rx 9C0 is a ten bit output bus used to transfer symbol pairs from the plc-s to a mac device, or to another plc-s. the ten bits are clocked to the mac device on the rising edge of bclk. rx 9C5 contain the most sig- nificant symbol and rx 4C0 contain the least significant symbol of the framed byte. bit 9 is the upper control bit and bit 4 is the lower control bit. rxpar receive data parity bit (output) rxpar is an output signal used to enhance error detec- tion on the rx bus. if there is an odd number of ones on rx 9C0 then rxpar will be one, and if there is an even number of ones on rx 9C0 then rxpar will be zero (even parity). when the plc-s is in bypass mode (that is when the data output on rx 9C0 is the data input on tx 9C0) rxpar is not calculated and is just the value input on txpar. rdat 4C0 receive data bus (input) rdat 4C0 is a five bit input bus used to transfer data from the pdr device to the plc-s. data is latched by the plc-s on the rising edge of rsclk. transmit data signals tdat 4C0 physical transmit data bus (output) tdat 4C0 is a five bit output bus used to transfer sym- bols from the plc-s to the pdt. the symbols are clocked to the pdt on the rising edge of lsclk. tx 9C0 transmit data bus (input) tx 9C0 is a ten bit input bus used to transfer symbol pairs from a mac device, or from another plc-s, to the plc-s. the ten bits are latched by the plc-s on the fall- ing edge of lsclk. bits 9C5 of the bus contain the first symbol to be transmitted on the fiber and bits 4C0 con- tain the second symbol. bit 9 is the upper control bit and bit 4 is the lower control bit. txpar transmit data parity bit (input) txpar is an input signal used to implement even parity on the tx bus. if there is an odd number of ones on tx 9C0 then txpar should be one and if there is an even number of ones on tx 9C0 then txpar should be zero. node processor interface signals int interrupt (output, active low) the int signal indicates an interrupt request from the plc-s. this signal is active until cleared by reading the intr_event register at address 17 (hex). cs chip select (input, active low) cs selects the plc-s for the current bus cycle. npaddr 4C0 node processor address bus (input) the npaddr 4C0 bus is a five bit input bus used to se- lect one of the registers in the plc-s for a read or write cycle.
amd p r e l i m i n a r y 3-13 AM79C864A np 15C0 node processor data bus (input/output, three state) the np 15C0 bus is a sixteen bit bi-directional, three- state data bus used to exchange data between the plc-s and the node processor. nprw node processor read/write (input) the nprw signal indicates whether the current bus cy- cle is a read (nprw = 1) or a write (nprw = 0) cycle. rst reset (input, active low, asynchronous) the rst signal provides a means of initializing the plc-s on power up. when asserted, the reset causes the following: n the various state machines are initialized: lsm-not active, pcm-off, pci-removed, repeat filter on repeat, node processor interface-not active. n all writable registers are cleared and all registers that are cleared on a read are cleared. n built-in self test C off n the fiber optic transmitter off ( fotoff ) signal is asserted, quiet symbols are transmitted on tdat, and tx is looped back onto rx. once rst is asserted low, it must remain asserted for at least twenty npclk cycles. when it is deasserted the plc-s is ready to begin its normal operation. assertion and deassertion are asynchronous. a warm reset (assertion of rst after the device is in operation) will cause device outputs to be unpredictable until the device is initialized. pdt and pdr interface signals lpbck loopback ( output, active low) the lpbck signal controls the receive multiplexer in the pdr device. if lpbck= 0, the mux selects its input from the pdt. if lpbck = 1, the mux selects its input from the fiber optic receiver. fotoff fiber optic transmitter off (output, active low) the fotoff signal, when asserted, causes the pdt to transmit quiet symbols. this signal is asserted whenever: n the fot_off bit, loopback bit, eb_loc_loop bit, lm_loc_loop bit in the plc_cntrl_a register (or) cipher_lpbck bit in plc_cntrl_c register is set. n the maint_ls field in the plc_cntrl_b register equal transmit quiet and the pcm is in the maint state and fotoff assertion timer expires, if enabled. n the physical connection management logic has set ls_request = transmit quiet line state and fotoff assertion timer expires, if enabled. n built-in self test is active. sdo signal detect (input, active high) the sdo signal is output by the pdr to indicate whether the fiber optic receiver is detecting an optical signal above its threshold. the inverted value of this signal is held in the plc_status_a register, and the lsdo bit in the intr_event register is set when sdo is asserted. test signals ptsto parametric test output (output) this is an internal parametric test output signal. this pin should be left unconnected. scano scan output (output) the scano signal is used as an output of the scan chain when the plc-s is in boundary scan serial test mode. test 2C0 plc-s test mode (input) the three test 2C0 input pins are used to select be- tween normal operating mode and three different test modes. the different operating modes are as follows: test 2C0 mode of device operation 0 0 0 normal operating mode 0 1 x normal operating mode 0 0 1 factory test mode (counter segmentation test) 1 0 scan input boundary scan serial test mode 1 1 0 boundary scan parallel test mode 1 1 1 all output pins except ptsto are high impedance
amd p r e l i m i n a r y 3-14 the supernet 2 family for fddi 1994 data book rrsclk reserved (input) this pin should be connected to vss. control and status signals ebferr elasticity buffer error (output, active high) ebferr indicates when an overflow or underflow con- dition occurs in the elasticity buffer. encoff encoder off (input, active high) the encoff signal turns off the encoding and decod- ing function of the plc-s. this allows for the transmis- sion of any symbol, including invalid symbols for diagnostic purposes. lsr 2C0 line state register (output) the lsr 2C0 signals directly output the line_st field of the plc_status_a register to ring test and monitor equipment. lsr 2C0 description 000 noise line state (nls) 001 active line state (als) 010 undefined 011 idle line state (ils4 C achieved after 4 idle symbols) 100 quiet line state (qls) 101 master line state (mls) 110 halt line state (hls) 111 idle line state (ils16 C achieved after 16 idle symbols) ulsb unknown line state (output) the ulsb signal directly outputs the unkn_line_st bit of the plc_status_a register to ring test and moni- tor equipment. scrm scrambler enable (input) this pin when held high will enable the stream cipher scrambling/descrambling function. if this pin is held low, then bit 0 of plc_cntrl_c register determines if stream cipher scrambling/descrambling function is enabled. power and ground v dd power (inputs) the v dd pins supply +5 v to the device. v ss ground (input) the v ss pins ground the device.
amd p r e l i m i n a r y 3-15 AM79C864A functional description node processor interface (npi) the node processor interface serves as the interface between an external node processor and the plc-s. the interface is a general purpose synchronous interface. the node processor interface is controlled by the npclk. in normal operation this clock is tied to the bclk. all signals of the npi must be synchronous with the npclk, that is the signals must be stable a setup time before and a hold time after a rising edge of the npclk. figure 1 illustrates the npi state machine. read cycle a read cycle is used by the node processor to read data from a plc-s register. normally the plc-s is unaf- fected by a read, although the intr_event, viol_sym_ctr, min_idle_ctr, and link_err_ ctr registers are cleared when read. a read cycle of one of the plc-s registers is initiated by the assertion of the cs signal which is sampled by the rising edge of npclk. once the cs signal is asserted the npaddr bus and nprw signals are sampled. the nprw signal should be high for a read and low for a write. at least one half npclk cycle after this edge, the plc-s will begin to drive the np bus to allow the chip driving the bus in the previous read or write cycle time to tri-state the np bus. after the next rising edge of npclk (the second rising edge after the assertion of cs ), the data on the np bus will be valid. it will remain valid until the second rising edge of npclk after the deassertion of cs . the plc-s will tri-state the np bus within 1/2 npclk cycle after this clock edge. the timing described above will allow a read cycle every 2 npclk periods. however, if the node processor needs to extend the read cycle and have the np bus valid longer than one clock cycle, it can delay the deassertion of the cs signal. for a minimum length read cycle (2 npclk periods), the node processor must deassert cs a setup time before the second rising edge of npclk following the assertion of cs . if cs remains asserted for a hold time after the second rising edge of npclk, again with respect to cs being asserted, the plc-s will continue to drive the np bus with valid data for two more rising edges of the npclk. when cs is kept asserted beyond the initial read cycle, the read cy- cle extends by two npclk periods. the cs signal is sampled on the second and each subsequent rising edge of npclk after the initial assertion of cs . the node processor can indefinitely extend the read cycle by maintaining the assertion of the cs signal. the node processor must deassert and then assert the cs signal for each unique read access. write cycle a write cycle is used by the node processor to write data into a plc-s control register. the node processor is normally allowed to write to any read-write or write-only register at any time except to the following registers xmit_vector, vector_length, tpc_load_ value, and tne_load_value due to special operating conditions imposed by the plc-s in their usage. if the node processor attempts a write on a read- only register or the special registers mentioned above at a wrong time, the plc-s sets the np_err bit in the intr event register. the plc-s will not modify the contents of the register accessed. the write cycle is very similar to the read cycle. the prin- cipal differences are as follows: n the nprw signal must be low while cs is asserted n the data to be written must be valid on the second rising edge of npclk after cs is asserted the node processor must tri-state the np bus within one half npclk period after the second rising edge af- ter the deassertion of cs . thus, by delaying the deassertion of the cs signal, the node processor can extend the write cycle and the time it has to tri-state the np bus. the deassertion of the cs signal has no effect on the plc-s during a write cycle. the plc-s will not attempt to write to a selected register more than once until the cs signal has been deasserted. thus, to ac- complish back to back writes, the node processor must deassert the cs signal before attempting the second write.
amd p r e l i m i n a r y 3-16 the supernet 2 family for fddi 1994 data book 15535b-5 idle write1 write2 write4 write3 write5 read1 read2 read4 read3 read5 cs = 1 cs = 1 cs = 0 cs = 0 cs = 0 cs = 0 drive np latch data cs = 1 cs = 1 latch address tri-state np cs = 0 nprw = 1 cs = 0 nprw = 0 latch address tri-state np cs = 0 nprw = 1 cs = 0 nprw = 1 cs = 0 nprw = 0 cs = 0 nprw = 0 cs = 1 nprw = x cs = 1 nprw = x tri-state np figure 1. node processor interface state machine
amd p r e l i m i n a r y 3-17 AM79C864A registers the plc-s contains twenty-six 16 bit registers ad- dressed from 00 to 1a (hex). these registers are listed in table 1. table 1. plc-s registers address (hex) name type 00 plc_cntrl_a read/write 01 plc_cntrl_b read/write 02 intr_mask read/write 03 xmit_vector read/write (note 1) 04 vector_length read/write (note 1) 05 le_threshold read/write 06 c_min read/write 07 tl_min read/write 08 tb_min read/write 09 t_out read/write 0a plc_cntrl_c read/write 0b lc_length read/write 0c t_scrub read/write 0d ns_max read/write 0e tpc_load_value write only (note 2) 0f tne_load_value write only (note 3) 10 plc_status_a read only 11 plc_status_b read only 12 tpc read only 13 tne read only 14 clk_div read only 15 bist_signature read only 16 rcv_vector read only 17 intr_event read only (note 4) 18 viol_sym_ctr read only (note 4) 19 min_idle_ctr read only (note 4) 1a link_err_ctr read only (note 4) notes: 1. writable only when the pcm_signaling bit in the plc_status_b register is not set. 2. writable only when the pcm is in the maint state. 3. writable only when the pcm is in the maint state and the noise_timer bit in the plc_control_a register is not set. 4. register cleared on read. plc-s control and status registers the control and status information for the plc-s is con- tained in four registers. plc-s control register a (plc_cntrl_a) plc_cntrl_a has address 00 (hex). it is readable and writable. all bits of this register are cleared with the as- sertion of rst . plc_cntrl_a is used for the following functions: n timer configuration n specification of pcm maint state options n counter interrupt frequency n plc-s data path configuration n execution of plc-s built in self test note that several bits of this register can only be written if the pcm is in the off or maint state. if this register is written when the pcm is in any other state these bits will remain unchanged. the plc_cntrl_a register bit assignments are listed in table 2.
amd p r e l i m i n a r y 3-18 the supernet 2 family for fddi 1994 data book - addr (hex) 00 noise timer tne-16 bit tpc-16 bit req- scrub vsym- -ctr- intrs mini- ctr- intrs loop back fot- off eb- loc- loop lm- loc- loop sc- bypass sc- rem- loop rf- disable run- bist plc_cntrl_a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15535b-6 ena_ par_ chk table 2. plc_cntrl_a bit name definition 15 reserved 14 noise_timer the noise_timer bit allows the noise timing function of the pcm to be used when the pcm is in the maint state. this function causes the tne timer to be loaded with the value in the ns_max register whenever the line state machine transitions from idle line state to noise line state, active line state or unknown line state. if the timer expires before idle line state is recognized, the tne_expired bit in the intr_event register is set. 13 tne_16bit when tne_16bit is set it causes the tne timer to operate as a 16 bit timer. in this mode the 2 bits of the tne clock divider are bypassed and the tne timer is incremented every 80 ns. tne_16bit can only be written if the pcm is in the off or maint state. 12 tpc_16bit when tpc_16bit is set it causes the tpc timer to operate as a 16 bit timer. in this mode the 8 bits of the tpc clock divider are bypassed and the tpc timer is incremented every 80 ns. tpc_16bit can only be written if the pcm is in the off or maint state. 11 req_scrub the req_scrub bit allows limited access to the scrub capability of the plc-s chip. if the pcm is in the maint state or if the config_cntrl bit in the plc_cntrl_b register is set then the req_ scrub bit controls the scrub mux. if req_scrub is set then idle symbols are sourced at the rx 9C0 output port. the output at the tdat 4C0 output port is controlled separately by the maint_ls field in the plc_cntrl_b register. this bit may be written at any time, but only takes effect when the pcm is in the maint state or if the config_cntrl bit in the plc_cntrl_b register is set. 10 ena_par_chk if this bit is set, then parity checking takes place on tx9C0 lines. if reset, then parity checking is disabled. note: plc-s supports even parity. 09 vsym_ctr_intrs the vsym_ctr_intrs bit controls when the vsym_ctr interrupt bit in the intr_event register is asserted. when vsym_ctr_intrs is set, the interrupt is generated only when the viol_sym_ctr overflows (reaches 256). when vsym_ctr_intrs is cleared, the interrupt is generated every time the viol_sym_ctr is incremented (whenever a violation symbol is detected). 08 mini_ctr_intrs the mini_ctr_intrs bit partially controls when the mini_ctr interrupt bit in the intr_event register is asserted. when mini_ctr_intrs is set, the interrupt is generated when the minimum idle gap counter portion of min_idle_ctr overflows (reaches16). when mini_ctr_intrs is cleared, the interrupt is generated every time the counter is incremented (whenever a minimum length idle gap is detected). note that this bit does not affect interrupts caused by the idle counter minimum detector portion of min_idle_ctr. 07 loopback when loopback is set, it causes the lpbck output pin to be asserted low. this, in turn, causes data to be looped back from the output of the pdt chip to the input of the pdr chip.
amd p r e l i m i n a r y 3-19 AM79C864A table 2. plc_cntrl_a (continued) bit name definition 06 fot_off the setting of this bit will cause the assertion of the fotoff output pin of the plc-s. read plc_cntrl_c register description for behavior of this signal when scrambling/ descrambling is enabled. 05 eb_loc_loop when eb_loc_loop is set, a loopback path is set up in the plc-s chip just prior to the framer. data from the plc-s transit path are looped back to the input of the framer. this loopback path is also set up when the plc-s is executing its built in self test. note that this bit also controls which clock the framer and elasticity buffer use. when it is not set, the recovered byte clock is derived from the rsclk input pin, and when it is set, the bclk is used. thus, when this bit gets set, a clock glitch could be created which could cause receive data to be indeterminate for a clock cycle, spurious interrupts, and unknown values in the event counters. eb_loc_loop can only be written if the pcm is in the off or maint state. 04 lm_loc_loop when lm_loc_loop is set a loopback path is set up in the plc-s chip such that data from tx 9C0 are passed through the plc-s transmit path and looped back to the input of the receive path just after the elasticity buffer at the lm local loopback mux. this loopback path differs from eb_loc_loop in that the framer and elasticity buffer are bypassed. lm_loc_loop can only be written if the pcm is in the off or maint state. 03 sc_bypass the sc_bypass bit provides limited control over the plc-ss data path by providing a physical bypass of the plc-s. if the pcm is in the maint state or if the config_cntrl bit in the plc_cntrl_b register is set, then the sc_bypass bit controls the bypass mux. if both sc_bypass and req_ scrub are asserted then rx 9C0 is driven with idle symbols. if sc_bypass is asserted and req_scrub cleared, then rx 9C0 is driven by the data entering the plc-s at the tx 9C0 input. otherwise, rx 9C0 is driven by the data entering the plc-s at the rdat 4C0 input. this bit may be written at any time, but only takes effect when the pcm is in its maint state or if the config_cntrl bit in the plc_cntrl_b register is set. sc_bypass req_scrub rx 9C0 set set idle set reset tx 9C0 reset reset rdat 4C0 reset set rdat 4C0 02 sc_rem_loop when sc_rem_loop is set, a remote loopback path is set up inside the plc-s where symbols from the receive data path are looped back onto the transmit data path, traversing all of both paths except for the receive data output latch and the transmit data input latch. if the pcm is in the maint state or if the config_cntrl bit in the plc_cntrl_b register is set, then the sc_rem_loop bit controls the remote loopback mux. this loopback is used by the pcm to control the configuration and can be used to monitor the ring or otherwise control configuration during normal operation. this bit only has effect if the eb_loc_loop, lm_loc_loop and cipher_lpbck bits are not set. this bit may be written at any time, but only takes effect when the pcm is in the maint state or if the config_cntrl bit in the plc_cntrl_b register is set. 01 rf_disable when rf_disable is set, it disables the repeat filter state machine in the plc-s. 00 run_bist when run_bist is set, it causes the plc-s to begin running its built in self test. the completion of bist is indicated via an interrupt. bist can be stopped before completion by clearing this bit. once bist has completed, this bit must be cleared and set again before bist will restart. for more detail, refer to pages 30 and 42 . reset plc-s before setting this bit.
amd p r e l i m i n a r y 3-20 the supernet 2 family for fddi 1994 data book plc-s control register b (plc_cntrl_b) plc_cntrl_b has address 01 (hex). it is readable and writeable. all bits of this register are cleared with the as- sertion of rst . plc_cntrl_b contains signals and re- quests to direct the process of physical connection management. it is also used to control the line state match interrupt. the plc_cntrl_b register bit assignments are listed in table 3. config cntrl 01 match ls match ls match ls match ls maint ls maint ls maint ls class s pc loop pc loop pc join long pc maint pcm cntrl pcm cntrl plc_cntrl_b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr (hex) 15535b-7 table 3. plc_cntrl_b bit name definition 15 config_cntrl the config_cntrl bit allows control over the scrub, bypass, and remote loopback datapath muxes while the pcm is in normal operation. if this bit is set, then the req_scrub, sc_bypass, and sc_rem_loop bits in the plc_cntrl_a register will have effect regardless of the state of the pcm. if this bit is not set then the req_scrub, sc_bypass and sc_rem_loop bits will only have effect if the pcm is in the maint state. 14C11 match_ls the match_ls field specifies line states to be compared with the currently detected line state (as defined by line_st in the plc_status_a register). when a match occurs, the ls_match interrupt bit in the intr_event register is asserted. each bit of match_ls corresponds to a line state. if more than one bit is set, the interrupt is signalled if any of the line states match the current line state. if no bits are set, the interrupt is signalled on any change in the line_st field or the unkn_line_st bit. it is defined as follows: match_ls description 0000 interrupt on any change in line_st or unkn_line_st 1xxx interrupt on quiet line state x1xx interrupt on master line state xx1x interrupt on halt line state xxx1 interrupt on idle line state in the above table, x means dont care. also idle line state refers to ils16, which is signalled only after sixteen idle symbols (eight idle bytes) have been received. 10C8 maint_ls the maint_ls field defines the line state the pcm will source while in the maint state. the pcm enters the maint state from the off state if the pc_maint bit is asserted. it is further defined as follows: maint_ls description 000 transmit quiet line state 001 transmit idle line state 010 transmit halt line state 011 transmit master line state 100 transmit quiet line state 101 transmit quiet line state 110 transmit pdr (transmit phy_data request)CCthe symbol stream at tx 9C0 is transmitted 111 transmit quiet line state
amd p r e l i m i n a r y 3-21 AM79C864A table 3. plc_cntrl_b (continued) bit name definition 07 class_s when class_s is set, signifying that the phy is a single attach station, the station will not be bypassed before the pcm gets to the active state. note that this bit has effect when the pcm is in normal operation. when the pcm is in the maint state, the req_scrub and sc_bypass bits in the plc_cntrl_a register control the bypass operation. this bit can only be changed when the pcm is in the off state. if this bit is written when the pcm is in any other state, the change will be ignored. 06C05 pc_loop pc_loop controls the loopback used in the link confidence test (lct). when it is set to a value other than zero and the pcm is in the next state, the pcm will perform the lct in one of three ways. the following table describes the action taken according to the value of the two bits: pc_loop description 00 no lct is performed 01 the pcm asserts transmit pdr. this assumes that protocol data units (pdus) will be input at tx(9C0). 10 the pcm asserts transmit idle. this causes the plc-s to source idle symbols. 11 the pcm asserts transmit pdr and sets up a remote loopback path in the plc-s. pc_loop should only be written after the pcm_code interrupt has been generated. if the pcm is not in the next state, or if pcm_signaling is set, then any value written to this field will be ignored. once pc_loop has been written, it must be cleared and then written again to perform another lct. 04 pc_join when pc_join is set and the pcm is in the next state, the pcm will transition to the join state and the pcm join sequence will be started. pc_join should only be written after the pcm_code interrupt has been generated. if the pcm is not in the next state or if pcm_signaling is set, then any value written to this field will be ignored. after this bit is set, it must be cleared and then set again to cause another transition from the next state to the join state. note that if pc_join is set after the lct has been started but before it has completed, then the lct will be aborted and the pcm join sequence started. 03 long when long is set, the pcm will perform a long lct; that is, it will continue the test until the processor issues a pc_signal (i.e., a write to xmit_vector register), pc_join, or other command. otherwise it will perform a lct, that is, it will stop the test after the length of time indicated in the lc_length register. in either case lct will stop whenever master line state or halt line state is detected, indicating that the neighboring station has completed its lct and has started signaling. 02 pc_maint when pc_maint is set, the pcm state machine transitions to the maint state if it is currently in the off state. if the pcm is not in the off state when this bit is written, and subsequently transitions to the off state, it will immediately transition to the maint state.
amd p r e l i m i n a r y 3-22 the supernet 2 family for fddi 1994 data book table 3. plc_cntrl_b (continued) bit name definition 01C00 pcm_cntrl pcm_cntrl controls the pcm state machine. when set to a value other than zero, it will cause the pcm to immediately make a transition to the break, trace or off state. the transition to the break or off state will occur regardless of the state the pcm is in at the time. the transition to the trace state will only be made if the pcm is in the active state, otherwise pcm_cntrl will be ignored. the following table describes the action taken according to the value of the two bits: pcm_cntrl description 00 the pcm state is not affected 01 the pcm goes to the break state (pc_start) 10 the pcm goes to the trace state (pc_trace) 11 the pcm goes to the off state (pc_stop) after a pc_start (pcm_cntrl=01) has been issued and before another one can be issued, pcm_cntrl must first be written with zero and then written with the pc_start value again. note that if the pcm goes to the break state for a reason other than writing pcm_cntrl (e.g. qls is received, or a timeout occurs), the pcm will not go to the connect state and will remain in the break state until pcm_cntrl is written with the pc_start value. if the pci is in the inserted state when pc_start or pc_stop is issued, scrubbing will be performed. if the pci is in the insert_scrub or remove_scrub state when pc_start or pc_stop is issued, the scrubbing will be completed before the pcm enters the break or off state.
amd p r e l i m i n a r y 3-23 AM79C864A plc-s control register c (plc_cntrl_c) plc_cntrl_c has address oa (hex). it is readable and writeable. bits 1 through 15 are cleared with the as- sertion of rst . bit 0 (cipher_enable) assumes the same value as scrm after rst is asserted. the plc_cntrl_c register bit assignments are listed in table 4. fotoff_ ctrl reserved sdoff_ timer sdoff_ timer sdon_ timer sdon_ timer fotoff_ ctrl plc_cntrl_c 15 14 13 12 11 10 9 8 15535b-8 7 6543210 cipher_ enable sdon_ enable sdoff_ enable reserved cipher_ lpbck addr (hex) 0a table 4. plc_cntrl_c bit name definition 15C14 reserved these two bits are reserved for diagnostic purposes and must be 0 for normal operation. 13C12 sdoff_timer these two bits are used to select the timing values shown for deasserting signal_detect enable bit is set and scrambler/descrambler is enabled either (by scrm or cipher_ enable) 00=0.76 m s 01=1.32 m s 10=2.52 m s 11=5.12 m s 11C10 sdon_timer these two bits are used to select the timing values shown for asserting signal_detect if sdon_ enable bit is set and scrambler/descrambler is enabled either by hardware or software. 00=0.84 m s 01=1.32 m s 10=2.52 m s 11=5.12 m s 9C8 fotoff _ctrl these two bits are used to control the assertion of fotoff signal of plc-s if scrambler/ descrambler is enabled either (by scrm or cipher_enable). the following timing delays are with respect to the time from which plc-s output scrambled quiet symbols on tdat lines. 00=timer is bypassed (i.e., fotoff is asserted at the same time when scrambled quiet symbols are output on tdat lines) 01=30 m s delay 10=50 m s delay 11=fotoff is never asserted 7 sdon_enable if this bit is set and scrambler/descrambler is enabled (by scrm or cipher_enable), then sdon_timer bits (11C10) will determine the delay for asserting the signal_detect signal. during this time, the descrambler is allowed to acquire synchronization of its input stream. 6 sdoff_enable if this bit is set and scrambler/descrambler is enabled (byscrm or cipher_enable ), then sdoff_timer bits (13C12) will determine the delay for deasserting the signal_detect signal. 5C2 reserved bits 5C2 are reserved and should be set to 0. 1 cipher_lpbck if this bit is set, then the output of the scrambler is looped back to the input of the descrambler (within plc-s). 0 cipher_enable this bit is used to enable and disable the scrambler/descrambler function if scrm (pin #41) is not asserted. if scrm is asserted, this bit is automatically set to 1. if scrm is not asserted, the value of this bit is determined by software. the default state (scrm not asserted) is 0.
amd p r e l i m i n a r y 3-24 the supernet 2 family for fddi 1994 data book plc-s status register a (plc_status_a) plc_status_a has address 10 (hex). it is read-only. it is used to report status information to the node proc- essor about the line state machine (lsm). the plc_status_a register bit assignments are listed in table 5. sym pr ctr 10 signal detect prev line st prev line st line st line st line st lsm state unkn line st sym pr ctr sym pr ctr plc_status_a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr (hex) 15535b-10 revision_id table 5. plc_status_a bit name definition 15C11 revision_id these bits give the revision identification. for am79864a (plc-s), these bits equal 11111. for am79c864 (plc), these bits equal 00000. 10 signal_detect this bit, when set, indicates that signal detect is deasserted. if sdo equals zero, then signal_detect is one; if sdo equals one, then signal_detect is zero. 09C08 prev_line_st this field contains the value of the previous line state whenever line state changes from quiet line state, master line state, halt line state or idle line state (ils16, where ils16 is achieved after 16 idle symbols) to another line state. when the line state changes from anything else, this field will not be updated. it is further defined as follows: prev_line_st description 00 quiet line state (qls) 01 master line state (mls) 10 halt line state (hls) 11 idle line state (ils16 C achieved after 16 idle symbols) 07C05 line_st this field contains the most recently recognized line state by the lsm. line_st is further defined as follows: line_st description 000 noise line state (nls) 001 active line state (als) 010 undefined 011 idle line state (ils4 C achieved after 4 idle symbols) 100 quiet line state (qls) 101 master line state (mls) 110 halt line state (hls) 111 idle line state (ils16 C achieved after 16 idle symbols) 04 lsm_state this field contains the state bit of the lsm state machine. 03 unkn_line_st this bit is the unknown line state bit from the lsm. since a minimum of sixteen symbols is required to satisfy the entry conditions of a line state (four symbols in the case of idle line state), the lsm uses this bit to indicate it is attempting to recognize a new line state. this bit is set to a one when the line state is unknown and reset to a zero when known. 02C00 sym_pr_ctr this field contains the lsm symbol pair counter. when the count reaches seven, indicating eight consecutive like symbol pairs, then current line state is set with the new line state and the unknown line state bit is reset. note that idle line state (ils4) is reached after just two idle symbol pairs.
amd p r e l i m i n a r y 3-25 AM79C864A plc-s status register b (plc_status_b) plc_status_b has address 11 (hex). it is read-only. it contains signals and status from the repeat filter and physical connection management state machine (pcm). the plc_status_b register bit assignments are listed in table 6. break reason rf state 11 pcm state pcm state pcm state pcm state pcm signal lsf rcf tcf break reason break reason plc_status_b rf state pci state pci state pci scrub 15535b-11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr (hex) table 6. plc_status_b bit name definition 15C14 rf_state this field contains the state bits of the repeat filter state machine. the states are defined as follows: rf_state name 00 repeat 01 idle 10 halt1 11 halt2 13C12 pci_state this field contains the state bits of the physical connection insertion state machine. the states are defined as follows: pci_state name 00 removed 01 insert_scrub 10 remove_scrub 11 inserted 11 pci_scrub the pci_scrub flag indicates that the scrubbing function is being executed, that is idle symbol pairs are being sourced on the rx output pins. 10C07 pcm_state this field contains the state bits of the physical connection management state machine. the states are defined as follows: pcm_state name 0000 pc0 (off) 0001 pc1 (break) 0010 pc2 (trace) 0011 pc3 (connect) 0100 pc4 (next) 0101 pc5 (signal) 0110 pc6 (join) 0111 pc7 (verify) 1000 pc8 (active) 1001 pc9 (maint) 1010C1111 reserved
amd p r e l i m i n a r y 3-26 the supernet 2 family for fddi 1994 data book table 6. plc_status_b (continued) bit name definition 06 pcm_signaling pcm_signaling is a flag from the pcm indicating that the xmit_vector register has been written. the xmit_vector and vector_length registers cannot be written when this flag is set. 05 lsf the line state flag is used by the pcm to indicate that a given line state has been received since entering the current state. it is cleared on every change of pcm state. 04 rcf the receive code flag is used by the pcm to indicate that the receive pseudo code has started execution. this flag is used to prevent the receive pseudo code from being started multiple times while in the next state. 03 tcf the transmit code flag is used by the pcm to indicate that the transmit pseudo code has started execution. this flag is used to prevent the transmit pseudo code from being started multiple times while in the next state. 02C00 break_reason this field indicates the reason for the pcm state machines last transition to the break state. it is defined as follows: break_reason description 000 the pcm state machine has not gone to the break state. 001 pc_start issued 010 tpc timer expired after t_out 011 tne timer expired after ns_max 100 quiet line state detected 101 idle line state detected 110 halt line state detected 111 reserved physical connection management (pcm) timers the pcm contains two timers, tpc and tne. both tim- ers have a clock divider circuit to reduce the frequency at which they are clocked. tpc timer the tpc timer is a 16-bit timer. in normal operation it is read-only by the node processor. tpc is read at address 12 (hex). when the pcm is in the maint state a value can be written to tpc by writing tpc_load_ value at address 0e. the tpc timer is incremented by the output of an 8-bit clock divider circuit. it is incre- mented every 20.48 m s (2 8 times 80 ns). the value in the tpc clock divider is contained in bits 7 through 0 of the clk_div register at address 14 (hex). the tpc timer is used while the pcm is attempting to establish a physical connection with a neighboring pcm. it is used to ensure that state transitions proceed at the desired rate. the timer is loaded with a twos complement value and counts up until it reaches zero. in normal operation the timer is loaded by the pcm from the tpc timing parameter registers, which contain the twos comple- ment of the time value in 20.48 m s units. at the same time the tpc timer is loaded, the tpc clock divider is loaded with zero. when the pcm is in the maint state, the tpc timer can be loaded directly from the node processor. the node processor accomplishes this by writing a 16-bit value which is loaded into the timer (the tpc clock divider is loaded with zero). the value written is the twos comple- ment of the time in 20.48 m s units. if the pcm is not in the maint state when a write is attempted to the tpc timer, the np_err bit in the intr_event register will be set and the timer will not be loaded. the timer may also be used in 16-bit mode, where the tpc clock divider is bypassed and the timer is incre- mented every 80 ns when in operation. in this mode the value loaded into the timer is the twos complement of the time remaining in 80 ns units. this feature, con- trolled by the tpc_16bit bit in the plc_cntrl_a reg- ister, is intended for test purposes, where it is desirable to run the timer for only short periods of time. tne timer the tne timer is a 16-bit timer. in normal operation it is read-only by the node processor. tne is read at ad- dress 13 (hex). when the pcm is in the maint state and the noise_timer bit in the plc_cntrl_a regis- ter is not set, a value can be written to tne by writing tne_load_value at address 0f. the tne timer is incremented by the output of a 2-bit clock divider circuit. it is incremented every 0.32 m s (2 2 times 80 ns).
amd p r e l i m i n a r y 3-27 AM79C864A the value in the tne clock divider is contained in bits 9 and 8 of the clk_div at address 14 (hex). the tne timer is used to time the length of (potential) noise events while the pcm is in the active state. the tne timer is started whenever the line state machine transitions from idle line state to noise line state, ac- tive line state, or unknown line state. if the timer ex- pires before the lsm recognizes idle line state again, the pcm transitions to the break state. the timer is loaded with a twos complement value and counts up until it reaches zero. in normal operation the timer is loaded by the pcm from the ns_max timing parameter register, which contains the twos comple- ment of the time value in 0.32 m s units, whenever the lsm leaves idle line state. at the same time the tne timer is loaded, the tne clock divider is loaded with zero. when the pcm is in the maint state the tne timer can be loaded directly from the node processor. the node processor accomplishes this by writing a 16-bit value which is loaded into the timer (the tne clock divider is loaded with zero). the value written is the twos comple- ment of the time in 0.32 m s units. if the pcm is not in the maint state when a write is attempted to the tne timer, the np_err bit in the intr_event register will be set and the timer will not be loaded. note that through use of the noise_timer bit in the plc_cntrl_a register, the tne timer can be used to time noise duration when the pcm is in the maint state without the timer having to be explicitly loaded by the node processor. the node processor should not at- tempt to load the tne timer when the noise_timer bit in the plc_cntrl_a is set. if this condition is vio- lated the np_err bit in the intr_event register will be set and the timer will not be loaded. the timer may also be used in 16-bit mode, where the tne clock divider is bypassed and the timer is incre- mented every 80 ns when in operation. in this mode the value loaded into the timer is the twos complement of the time remaining in 80 ns units. this feature, con- trolled by the tne_16bit bit in the plc_cntrl_a reg- ister, is intended for test purposes, where it is desirable to run the timer for only short periods of time. physical connection management timing parameters the pcm uses a number of different timing parameters while forming a physical connection. the parameters are programmable and must be written by the node processor. the registers are readable at any time. the parameters are 16 bits in length and are loaded into the tpc timer. they hold the twos complement of the time in 20.48 m s (2 8 times 80 ns) units. they have a maximum value of about 1.34 seconds (2 16 times 20.48 m s). when the tpc timer is in 16-bit mode the timing parameters are the twos complement of the time in 80 ns units and can have a maximum value of about 5.24 ms (2 16 times 80 ns). in addition to the tpc timing parameters, there is one timing parameter used by the tne timer. unlike the tpc timing parameters, ns_max holds the twos com- plement of the time in 0.32 m s (2 2 times 80 ns) units. it can have a maximum value of about 20.97 ms (2 16 times 0.32 m s). when the tne timer is in 16-bit mode, ns_max is the twos complement of the time in 80 ns units and can have a maximum value of about 5.24 ms (2 16 times 80 ns). table 7 summarizes the pcm timing parameters. minimum connect state time register (c_min) the minimum connect state time (c_min) register has address 06 (hex). it has a recommended value of 1.6 ms (ffb2 hex in 2s complement). this is the minimum time required to remain in the connect state to assure that the other end has recognized halt line state. minimum line state transmit time register (tl_min) the minimum line state transmit time register (tl_min) has address 07 (hex). it has a recommended value of 0.03 ms (fffe hex in 2s complement). this is the minimum time required to transmit a line state be- fore advancing to the next pcm state. minimum break time register (tb_min) the minimum break time (tb_min) register has ad- dress 08 (hex). it has a recommended value of 5 ms (ff10 hex in 2s complement). when pcm performs a break (in state break), the break shall be of adequate length to allow time for a response to be seen on the in- bound physical link. this time allows for the possibility of a bypass failure mode in this or a neighboring station that could cause four phys to be connected in a loop and produce an invalid response to the break. the mini- mum break time guarantees that in this case the re- sponse to the break will propagate around the loop and be seen on the inbound link. signaling timeout register (t_out) the signaling timeout (t_out) register has address 09 (hex). it has a recommended value of 100 ms (eced hex in 2s complement). a response from a neighboring pcm must be received by t_out. when a response is expected and no transition is made in t_out time, a transition is made to the break state. link confidence test time register (lc_length) the link confidence test (lct) time register (lc_length) has address 0b (hex). this register specifies the time duration of the lct and limits the du- ration of loopback to prevent deadlock. it has a recom- mended value of 50 ms (f676 hex in 2s complement)
amd p r e l i m i n a r y 3-28 the supernet 2 family for fddi 1994 data book for the short lct. for medium lct, it has a recom- mended value of 500 ms (a0a2 hex in 2s complement). scrub time register (t_scrub) the scrub time (t_scrub) register has address 0c (hex). it has a recommended value of 3.5 ms. t_scrub is the same as the mac tvx time. its use is described in the physical connection insertion process functional description. noise time register (ns_max) the noise time (ns_max) register has address 0d (hex). it has a recommended value of 2 ms. ns_max is the maximum length of time that noise is tolerated be- fore a connection is broken down. table 7 summarizes the recommended values for the timing parameter registers. also shown is the 2s com- plement, hexadecimal equivalent of the recommended value and the timer used for the parameter. table 7. summary of pcm timing parameters recommended register value address parameter value (ms) (2's comp/hex) timer (hex) c_min 1.6 ffb2 tpc 06 tl_min 0.03 fffe tpc 07 tb_min 5 ff10 tpc 08 t_out 100 eced tpc 09 lc_length 50 f676 tpc 0b lc_length 500 a0a2 tpc 0b t_scrub 3.5 ff6d tpc 0c ns_max 2 e796 tne 0d physical connection management bit signaling registers the plc-s contains three registers used by the pcm to perform bit signaling. bit signaling is the mechanism the pcm uses to transfer information to the pcm in the neighboring station. transmit vector register (xmit_vector) the transmit vector register has address 03 (hex). it is readable and writable. all bits of the register are cleared with the assertion of rst . the pcm_signaling bit must not be asserted in order to write to this register. if pcm_signaling is asserted when a write is at- tempted, the register will not be written and the np_err bit in the intr_event register will be set. this register is readable at any time. the transmit vector consists of from one to sixteen bits of data to be transmitted to the neighboring pcm. bits are transmitted one at a time by the bit signaling mecha- nism. a one bit is represented by the transmission of halt line state and a zero bit by master line state. bit 0 of this register is the first bit to be transmitted, then bit 1, etc., up to the number of bits specified in the vector_length register. writing this register causes pcm_signaling to be as- serted. therefore, the vector_length register must be initialized before this register is written. transmit vector length register (vector_length) the transmit vector length register has address 04 (hex). it is readable and writable. all bits of the register are cleared with the assertion of rst . the pcm_sig- naling bit must not be asserted in order to write to this register. if pcm_signaling is asserted when a write is attempted, the register will not be written and the np_err bit in the intr_event register will be set. this register is readable at any time. bits 15 through 4 of this register are unused. any value written to these bits will be ignored. these bits will al- ways be read as zeros. bits 3 through 0 of this register contain the number of bits in the xmit_vector register to transmit. the value in this field (0 to 15) is actually one less than the number of bits to transmit (1 to 16). receive vector register (rcv_vector) the receive vector register has address 16 (hex). it is read-only. the receive vector consists of from one to sixteen bits of data received from the neighboring pcm. bits are re- ceived at the same time bits are being transmitted. as bit n is being transmitted from the transmit vector, bit n is received and placed in the receive vector register. if halt line state is received, then bit n is a one, and if master line state is received then bit n is a zero. bit 0 of this register is the first bit received, then bit 1, etc., up to the number of bits specified in the vector_ length register. although this register is readable at any time, if pcm_signaling bit is asserted when this register is read the data may be incomplete. event counters the plc-s contains three event counter registers and one threshold value register (used for gathering infor- mation about errors occurring on its associated physical link and for monitoring idle symbol gaps between packets). violation symbol counter (viol_sym_ctr) the violation symbol counter has address 18 (hex). it is read-only and is cleared whenever it is read as well as when rst is asserted. the high order 8 bits of the regis- ter will always be read as zeros. the low order 8 bits will contain the counter value. the vsym_ctr bit in the
amd p r e l i m i n a r y 3-29 AM79C864A intr_event register is set whenever the counter increments or whenever the counter overflows (reaches 256), depending on the setting of the vsym_ctr_intrs bit in the plc_cntrl_a register. when the counter overflows it wraps to zero and contin- ues to count. the violation symbol counter is incremented whenever the 4b/5b decoder in the plc-s decodes a violation symbol. see the decoder description for the symbols considered to be violation symbols by the decoder. they are represented as a v in table 15. minimum idle counter (min_idle_ctr) the minimum idle counter has address 19 (hex). it is read-only and is cleared whenever it is read as well as when rst is asserted. the high order 9 bits of the regis- ter will always be read as zeros. bits 6 through 4 of the counter contain the value in the idle counter minimum detector. this is the minimum number of inter-packet idle symbol pairs seen since the counter was last reset. it gets reset to 7. whenever the value changes to a lower value, the mini_ctr bit in the intr_event register is set. the idle symbol pair count definitions are given in table 8. table 8. idle counter minimum detector min_idle_ctr 6C4 idle symbol pair count 100 7 or more 101 6 111 5 110 4 010 3 011 2 001 1 000 0 bits 3 through 0 of the counter contain the value in the minimum idle gap counter. this is the number of times the minimum number of inter-packet idles has been seen since the last reset. it gets reset to 1. the mini_ctr bit in the intr_event register is set when- ever the counter increments or whenever the counter overflows (reaches 16), depending on the setting of the mini_ctr_intrs bit in the plc_cntrl_a register. when the counter overflows, it remains at 16. the mini- mum idle occurrence count definitions are given in table 9. table 9. minimum idle gap counter minimum idle min_idle_ctr 3C0 occurrence count 0000 1 1000 2 1100 3 0100 4 0101 5 0111 6 1111 7 1110 8 1010 9 0010 10 0011 11 0001 12 1001 13 1101 14 0110 15 1011 16 link error event counter (link_err_ctr) the link error event counter has address 1a (hex). it is read-only and is cleared whenever it is read as well as when rst is asserted. it is an 8-bit counter contained in bits 7 through 0 of the register. bits 15 through 8 of the register will always be read as zeros. the le_ctr bit in the intr_event register is set whenever the counter reaches the value contained in the le_threshold register. the counter will continue to count past this point. when the counter overflows (reaches 256), it wraps to zero and continues to count. the link error event counter is part of the link error monitor (lem) and is implemented in the plc-s. the lem monitors bit error rate (ber) of an active link and detects and isolates physical links having an inadequate ber, e.g. due to a marginal link quality, link degradation or connector unplugging. in addition to the counter, the plc-s also contains logic to detect link error events. link error events are defined in table 12.
amd p r e l i m i n a r y 3-30 the supernet 2 family for fddi 1994 data book link error event threshold register (le_threshold) the link error event threshold register has address 05 (hex). it is readable and writeable and is cleared on the assertion of rst . bits 7 through 0 of this register contain a value that controls when the le_ctr bit in the intr_event register is set. whenever the value in the link_err_ctr reaches the value contained in this register the le_ctr bit will be set. bits 15 through 8 are ignored and will always be read as zeros. interrupt registers the plc-s has two interrupt registers which correspond bit-for-bit. one of the registers contains bits set by inter- rupt events and the other a mask which enables or dis- ables the assertion of the int pin due to a corresponding interrupt event. interrupt event register (intr_event) the interrupt event register (intr_event) has ad- dress 17 (hex). it is read-only and is cleared whenever it is read, as well as when rst is asserted. it is used by the plc-s to report events to the node processor. indi- vidual bits are set by the plc-s for the particular event occurrences. when an interrupt is generated (via the int pin), the node processor should read this register to identify the source(s) of the interrupt. note that while the run_bist bit in the plc_cntrl_a register is set, all interrupts are masked (prevented from asserting the int pin) except bist_done. since this is the only interrupt that can occur in this situation, bist_done need not occupy a bit in the intr_event register. the interrupt is cleared by clearing the run_bist bit in the plc_cntrl_a register. the intr_event register bit assignments are listed in table 10.
amd p r e l i m i n a r y 3-31 AM79C864A np err addr (hex) 17 lsdo ie ctr mini ctr vsym ctr phyinv ebuf err tne expired tpc expired pcm enabled pcm break self test trace prop pcm code ls match parity err intr-event 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15535b-12 table 10. intr_event register bit name definition 15 np_err an event indicating that the node processor has requested a read or write to an invalid register. this case includes a write to a read-only register (such as this one), a read of a write-only register, a write to a xmit_vector or vector_length register when pcm_signalling is set, a write to the tpc timer register while the pcm is not in the maint state, and a write to the tne timer register while the pcm is not in the maint state or noise_timer is set. 14 lsdo this bit is set whenever sd0 pin is asserted. 13 le_ctr an event indicating that the link error event counter has reached the value contained in the le_threshold register. 12 mini_ctr indicates that either of two events has occurred in the min_idle_ctr: the idle counter minimum detector has changed to a lower value; or, the minimum idle gap counter has incremented or overflowed, depending on the mini_ctr_intrs bit in the plc_cntrl_a register. 11 vsym_ctr an event indicating that a violation symbol counter has incremented or overflowed, depending on the vsym_ctr_intrs bit in the plc_cntrl_a register. 10 phyinv an event indicating that the physical layer invalid signal has been asserted. 09 ebuf_err an event indicating that the elasticity buffer has detected an overflow or underflow. 08 tne_expired an event indicating that the tne timer has expired, i.e. reached zero. 07 tpc_expired an event indicating that the tpc timer has expired, i.e. reached zero. 06 pcm_enabled an event indicating the pcm has asserted sc_join, has completed scrubbing, and is in the active state. 05 pcm_break an event indicating the pcm has entered the break state. 04 self_test an event indicating quiet or halt line state has been received while the pcm is in the trace state. 03 trace_prop an event indicating that master line state has been received while the pcm is in the active or trace state. 02 pcm_code an event indicating the pcm has completed transmitting the last bit in the vector written to the xmit_vector register and has received the corresponding bit of the rcv_vector, or that the link confidence test has completed. in the case where signalling has completed, pcm_code will not be set until the rcf flag has been set again. 01 ls_match an event indicating that the line state detected equals the line state in the match_ls field of the plc_cntrl_b register. 00 parity_err an event indicating that a parity error has been detected on the tx 9C0 input pins. this bit will not be set if ena_par_chk bit in plc_cntrl_a register is cleared.
amd p r e l i m i n a r y 3-32 the supernet 2 family for fddi 1994 data book interrupt mask register (intr_mask) the interrupt mask register (intr_mask) has ad- dress 02 (hex). it is readable and writeable. it allows the disabling of interrupts caused by specific events. the intr_mask contains a bit that corresponds to each bit of the intr_event register that, when clear, prohibits that condition from causing an interrupt to the node processor. for each set bit, the setting of the corre- sponding bit in the intr_event will generate an inter- rupt to the node processor via the int pin of the plc-s. note however, that the operation of a bit in the intr_event remains unchanged by the state of the corresponding bit in the intr_mask. all bits of this reg- ister are cleared with the assertion of rst . np err 02 lsdo ie ctr mini ctr vsym ctr phyinv ebuf err tne expired tpc expired pcm enabled pcm break self test trace prop pcm code ls match parity err intr-mask 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15535b-13 addr (hex) built in self test register in addition to a bit in the plc_cntrl_a register and a bit in the intr_event register, built in self test re- quires one register. built in self test signature register (bist_signature) the built in self test signature register (bist_signa- ture) has address 15 (hex). it is a 16 bit, read-only reg- ister that contains the resultant signature after execution of the chips self test. after bist has been completed (signaled by the int pin being asserted), this register should be read and its contents compared against the known good signature for the plc-s to determine whether the chip has passed its self test. the value of the bist signature is 5b6b (hex). framer the framer accepts five bit wide parallel data as well as the recovered clock from the physical data receiver (pdr) chip. generally, data received by the framer is not framed into proper fddi symbols. the framer is used to align the incoming data to form proper symbols before the data is passed onto the elasticity buffer. a starting delimiter that is used at the beginning of each frame is detected by the framer and used to determine proper symbol boundaries for the data. the framer has been designed such that the starting delimiter (the jk symbol pair) can be detected independent of previous framing. elasticity buffer the purpose of the elasticity buffer is to perform the necessary buffering in order to allow the passing of data between different fddi stations with independent sta- tion clocks. the elasticity buffer consists of an 80-bit buffer and some control circuitry. the buffer is used to compensate for the differences in the transmit and re- ceive clock frequencies in the station. data is clocked into the buffer by the recovered byte clock and clocked out of the buffer by the byte clock. the recovered clock is also used to drive all the input circuitry including the in- put controller and the local input pointer. the byte clock is used to drive the output circuitry including the output pointer, the output controller, the overflow/underflow detection circuitry and the output buffer. note that the elasticity buffer uses a different version of the byte clock than the rest of the plc-s chip. this version is gener- ated on chip from lsclk. smoother operation the smoother resides in the elasticity buffer. the main purpose of the smoother is to add and delete idle sym- bols into the data stream when the smoother detects an inadequate or a surplus number of idles between frames. the smoother function is necessary because the elas- ticity buffer may delete symbols from the preamble of a frame. if multiple phy elasticity buffers delete symbols from the same preamble, then the number of idle sym- bols in that preamble can reach a value resulting in a loss of that frame. this may happen because according to the ansi phy document, n an elasticity buffer is not required to recenter on preambles shorter than four symbols n mac is not required to repeat frames with pream- bles shorter than two symbols n mac is not required to copy frames with pream- bles shorter than twelve symbols the smoother absorbs surplus symbols from longer preambles and redistributes them into shorter pream- bles. the smoothing function is capable of inserting ad- ditional preamble symbols into repeated preambles shorter than fourteen symbols. the smoother attempts to maintain 7 idle bytes (or 14 idle symbols) between frames. if there are less than 7 idle bytes the smoother may inject idle bytes onto the data path. if there are more than 7 idle bytes in the preamble the smoother may delete at least one idle byte of the longer preamble.
amd p r e l i m i n a r y 3-33 AM79C864A line state machine (lsm) in the fddi network, a special group of symbols called line state symbols (q C quiet, h C halt, i C idle) are transmitted to establish the physical connection be- tween neighboring stations. these line state symbols are unique in that they may be recognized independ- ently of symbol boundaries. the lsm constantly monitors symbol pairs coming from the elasticity buffer. the current symbols pair is en- coded (enc_csp) and compared to the encoded value of the previous symbol pair (enc_psp). the symbol pairs are counted by the symbol pair counter (sym_pr_ctr C bits 2C0 in the plc_status_a register) until a line state is reached. once a line state is reached the sym_pr_ctr is stopped, the new line state (line_st C bits 7C5 in the plc_status_a register) is stored and the unkn_line_st bit is reset to zero. upon receiving the first symbol pair that is not identical to the previous symbol pair (and is not a jk or noise symbol pair) the sym_pr_ctr is started and unkn_line_st is set to 1 until conditions for the next line state are met. the recognition of these line states is reported to the pcm, which uses this information for insertion and removal of the station from the ring, ring recovery and maintenance. a change in the value of line_st is re- ported to the node processor by means of an interrupt which can be enabled or disabled by setting the match_ls bits in the plc_cntrl_b register. the lsm is reset into the not_active state with line_st = nls, unkn_line_st = 0, sym_pr_ctr = 000 and prev_line_st = qls. the function of the lsm state machine is described in table 11. table 11. lsm state descriptions state description lsm0 this is the not active state. the lsm is in this state whenever line_st equals anything other than als. a transition to lsm1 will occur whenever enc_csp = jk. lsm1 this is the active state. the lsm will stay in this state only if enc_csp = jk, data, or ii (if enc_cps = i i then only if enc_psp not = i i). anything else will cause a transition to lsm0. link error monitor (lem) the link error monitor provides an indication of the in- bound link quality to the physical connection manage- ment entity. the pcm uses this information to determine if the link confidence test passes to establish a new connection. once a link is active the pcm continually runs a link error monitor test to detect and isolate links having an inadequate bit error rate. the lem hardware consists of a detector, accumulator and threshold element. the detector is a state machine which constantly monitors incoming symbol pairs on the receive path. when link error events are detected they are counted by the 8-bit link error event counter (link_err_ctr). when the link_err_ctr matches the count written to the link error event threshold register (le_threshold) the le_ctr bit in the intr_event register is set. a link error event is defined in table 12 below. note that a number following an h or v symbol indicates the value of that symbols encoding. for instance, h2 is the symbol 00010, v5 is the symbol 00101, etc. table 12. lem error events noise events exceptions transition from idle line when the symbol pair state to noise line state or which causes the transition is unknown line state followed by: qq, qh, hq, or hh when in active line state, none detection of the symbol pair: xv, vx, j ~k, ~jk, or i d where: v = h1, h2, h8, h16, v3, v5, v6, v12, or j v = h1, h2, h8, h16, v3, v5, v6, v12, or k d = n, r, s, or t x = dont care ~k = not k; ~j = not j when in active line state, detection of the symbol pair: none i i followed by d x i i followed by i d other transitions from active when the symbol pair line state to noise line state h4 h4 which causes the or unknown line state transition is followed by: h4 q, q h4, i i, h4 i, or jk physical connection management (pcm) connection management (cmt) defines the operation of physical layer (phy) insertion and removal, and the connection of phy entities to the media access control (mac) entities. physical connection management (pcm) is a subset of cmt. fundamental to this task is the management of a connection between two physical attachments (phys) in adjacent stations. it is the job of the pcm state machines in both stations to cooperate in forming a connection between the two phys within the rules established by the connection management.
amd p r e l i m i n a r y 3-34 the supernet 2 family for fddi 1994 data book the fddi smt ansi standard defines the following types of physical attachment: a. dual ring phy entity connected to primary ring in, secondary ring out b. dual ring phy entity connected to secondary ring in, primary ring out m. concentrator phy entity type master to provide connection within the concentrator tree s. single attachment phy entity type slave, intended to be attached to a phy of type m within a concentrator tree. figure 2 illustrates different connection types. cmt defines the type of physical connection between two physical attachments. pcm consists of two entities; the pcm state machine and the pcm pseudo code. the plc-s chip implements the state machine, while the pseudo code is implemented in smt software. smt software decides the acceptability of connections and communicates it to the neighboring phy. secondary ring primary ring 15535b-14 b a m m m dac concentrator b a mm m dac concentrator s s s s s mmm sac concentrator ss s s sas sas sas sas sas sas sas end stations full duplex connection end stations end stations primary ring secondary ring a-b connection sas m-s connection m-s connection figure 2. illustrations of connection types
amd p r e l i m i n a r y 3-35 AM79C864A the physical connection insertion (pci) state machine works in conjunction with the pcm state machine. it controls ring scrubbing and the insertion and removal of a station on the ring. pcm operation the plc-s implements the pcm state machine as specified in the ansi fddi smt standard. by only al- lowing a specific set of connection types, cmt secures a deterministic ring topology, independent of the se- quence of station power on, etc. the primary purpose for the pcm is to enforce these allowable connections. the local pcm announces its attachment type to the re- mote pcm and listens for the type of attachment from the remote pcm. if they are compatible, the local pcm accepts the connection, reporting the type of connection to the station configurator. once the connection type has been established, the two pcms share in testing the pair of physical links between them. if this is successful, the link can then be configured into the ring. the bit sig- naling protocol is implemented in a fashion which re- duces the software processing overhead considerably while at the same time allow enough flexibility to change the actual pseudo code. pcm state machine the pcm state machine implements the connection se- quence for establishing the physical connection into the ring. the state machine is as described in the smt document. the pcm state machine uses various timers whose expiration values are programmable by the vari- ous time registers. the time registers that are relevant to the pcm state machine are the minimum connect state (c_min), minimum line state transmit time (tl_min) minimum break (tb_min), signalling timeout (t_out), link confidence test (lc_length)and noise time (ns_max). the current state of pcm is readable through the plc_status_b register. the pcm state machine is started by pc_start signal from the node processor as indicated by pcm_cntrl bits of plc_cntrl_b. the pcm state machine can be brought to the off state (stop connection) also by pro- gramming pcm_cntrl bits of plc_cntrl_b. pcm flags that are readable by the node processor through the status register of plc-s include line state flag (lsf), receive code flag (rcf) and transmit code flag (tcf). once the connection is established and the ring is scrubbed, pcm indicates the event through the pcm enabled bit of the intr_event register. the function of the pcm state machine is described in table 13. pseudo code bit signaling (pcs) as a part of the pcm process, before the connection is established, a sequence of bits are communicated through the physical link. these bits as defined in the standard convey the following information: n normal or escape sequence (escape sequence is not defined by the standard) n the type of physical connection (slave, master, peer a or peer b) n the acceptance of the connection n the length of the link confidence test (lct): short, medium, long or extended n mac for lct n lct pass/fail n mac loopback n mac output connected to this phy the above information is conveyed in the first 10 bits of the standard pseudo code bit signalling sequence. if more bits are needed, more information up to a maxi- mum of 16 bits can be sent through this process. the normal operation of the pcm is as follows. when the pcm is in the off state, all the parameter registers and the configuration registers are loaded with the ap- propriate values. the pc_start is written into the plc_cntrl_b register. the vector_length reg- ister is then written with value n-1 (n = the number of bits to be transmitted). next, the xmit_vector register is written with the bit pattern which is to be transmitted. the pcm then transitions through the break, con- nect and next states. note: the vector_length and xmit_vector register has to be written after pc_start and before tb_min timer expires. it then transitions back and forth between the next and the signal states until all the bits in the xmit_vector register are transmitted. it causes master line state to be sourced to signal a zero bit and halt line state to be sourced to signal a one bit. while it transmits all the bits it also receives the corresponding bits from the remote station and forms a receive vector which is stored in the rcv_vector register. when all the bits are transmit- ted the pcm_code interrupt bit is set. the node proc- essor can then read the rcv_vector register. ( note : the pcm is still in the next state). if for any reason (other than pc_start) the pcm state machine transitions to the break state, then a pc_start has to be issued before the connection proc- ess can begin again. this is to allow the vec- tor_length and the xmit_vector to be re-initialized. also, any transition to the break state sets the pcm_break interrupt and writes the reason for the transition in the break_reason field in the plc_status_b register. typically, three bits are written into the xmit_vector register in the beginning. after they are received, the re- ceived bits are read by the node processor to know the connection type. then the node processor decides if the
amd p r e l i m i n a r y 3-36 the supernet 2 family for fddi 1994 data book connection is acceptable and flags the next bit. on re- ceipt of the corresponding bit from the neighbor, the node processor decides the length of the link confi- dence test and communicates it through the next two bits. on receipt of the corresponding bits from the neigh- bor, the node processor communicates if it wants to per- form lct through the mac. after receipt of corresponding bit from the neighbor, the lct is per- formed. if the length of the lct is longer, then the node processor will set the long bit in the plc_cntrl_b register. if long bit is set, the node processor has to is- sue a pc_signal command to progress the sequence and communicate the status of lct in the next bit. on receipt of the corresponding bit from the neighbor, the mac loopback bit is sent. on receipt of mac loopback bit from the neighbor, the mac loop- back is performed based on the bit information. once the mac loopback is finished, the last bit is commu- nicated indicating if the mac output is going to be con- nected to this phy. after the lct is completed (i.e. after lc_length, or after halt or master line state is received) the pcm_code interrupt is set. if the node processor de- cides to transmit more signaling bits it should load the vector_length with a new value of n and then the xmit_vector register with the bit pattern to be trans- mitted. the pcm again starts transmitting these bits and alternates between next and signal states until all bits are transmitted upon which the pcm_code inter- rupt is set again. this sequence continues until all the bits are transmitted and the node processor writes pc_join in the plc_cntrl_b register. the pcm then leaves the next state and enters the join state. setting these bits has no effect when the pcm is not in the next state or when the pcm_signaling bit is set. however, if this bit is set even though lct is not finished yet, then lct will be aborted and the pcm join sequence will be initiated. noise detection mechanism the tne timer in the pcm times the period between the receptions of the idle line state. this timer is loaded with the ns_max parameter when line state machine leaves the idle line state. the tne timer keeps count- ing the noise until idle line state is again detected. while in the active state if this timer expires then the pcm will break the link and transition to the break state. in the active state the tne timer starts count- ing noise only after lsf is set. if pc_trace is set and the tne timer expires in the same cycle then the transition to the trace state is taken. this timer is ignored in all the pcm states except the active state. noise in maint state if the noise_timer bit in the plc_cntrl_a register is not set, then the node processor can write the tne timer if the pcm is in maint state. if the noise_tim- er bit is set, then the tne timer is used in the maint state to time the noise as described above. if the tne timer expires, then the tne_expired bit in the intr_event register is set. operation in trace state in the active state if trace propagation (i.e., receipt of master line state) is detected then the trace_prop interrupt is set. in the active state if pc_trace is re- ceived and a transition is made to the trace state then the station remains inserted, master line state is sourced on the tdat(4C0) port, and no scrubbing is performed. again in this state if master line state is de- tected, the trace_prop interrupt is set. if quiet line state or halt line state is detected, then the self_test interrupt is set.
amd p r e l i m i n a r y 3-37 AM79C864A table 13. pcm state description state description pc0(off) the pcm enters the off state whenever the rst pin is asserted or whenever the pcm_cntrl field of the plc_cntrl_b register is set to 11 (pc_stop). the pcm stays in this state until pc_start is issued or the pc_maint bit is set. pc1(break) this is the entry point in the start of a pcm connection. the pcm enters this state when pc_start is issued, or while it is in the process of forming a connection when any of various error conditions occur (such as receipt of quiet line state, a timeout, etc.). pc2(trace) the trace state is issued to localize a stuck beacon condition. it is entered when pc_trace is issued while the pcm is in the active state. pc3(connect) this state is used to synchronize the ends of the connection for the signaling sequence. it is entered from the break state. pc4(next) this state is used to separate the signaling performed in the signal state and to perform the link confidence test. it is entered from the connect state or signal state. pc5(signal) in this state individual bits of information are communicated across the connection by transmitting either halt symbols or alternating halt and quiet symbols (master line state). the pcm transmits and receives bits of information at the same time. this state is entered from the next state. pc6(join) this state is the first of three states that leads to an active connection. it is entered from the next state. pc7(verify) this state is the second state in the path to the active state. it will not be reached by a connection that is not synchronized. pc8(active) the active state is the state where the phy has been incorporated into the ring. it is entered from the verify state. pc9(maint) this state is used to override the normal pcm operation for test purposes or so that the pcm operation may be done completely in software. in this state the data path configuration and the transmit data stream are controlled by the node processor. pci operation the pci state machine works in conjunction with the pcm state machine to control the data paths of the plc-s on the mac side (the rx 9C0 and tx 9C0 paths). there are three primary functions of the pci state machine: n provide a bypass path between tx 9C0 and rx 9C0 n provide a scrubbing function upon the insertion and removal of a station from the ring n provide a direct path between the pdt/pdr and the mac the operation of the pci state machine depends on whether the class_s bit in the plc_cntrl_b regis- ter is set and whether the pcm state machine is in the maint state. pci operation for non-class s type station after a reset the pci state machine will be in the re- moved state. if the station is not of type class s, then the plc-s will be in the bypass mode where the data in- put on tx 9C0 is directly output on rx 9C0. when the pcm state machine enters the active state and asserts the sc_join flag, the pci state machine enters the insert_scrub state and idle symbol pairs are sourced on rx 9C0. at the same time, the pcm state machine causes idle symbols to be output on tdat 4C0. the pci state machine remains in the insert_scrub state for t_scrub length of time, after which it enters the inserted state. upon entering the inserted state, the pcm_enabled interrupt is asserted. in this state, a direct path exists from tx 9C0 to tdat 4C0. if for some reason the connection is broken and the pci state machine enters the remove_scrub state, idle symbol pairs are sourced on rx 9C0. because the pcm state machine is in the break state, quiet symbols are sourced on tdat 4C0. while scrubbing is being per- formed, the pcm state machine will not reCstart the con- nection process. the pci state machine remains in the remove_scrub state for t_scrub length of time and then enters the removed state. note that if the connection is broken while the pci state machine is in the insert_scrub state, scrubbing will
amd p r e l i m i n a r y 3-38 the supernet 2 family for fddi 1994 data book continue for t_scrub length of time and then enter the removed state. pci operation for class s type station for a class s type station, the pci operation is same as above with one exception. normally, for a non-class s type station, pci will be in removed state at reset, but for a class s type station, pci will be in the inserted state. thus, before entering insert_scrub or after leaving remove_scrub, rather than putting the plc-s in the bypass mode, phy_invalid is output on rx 9C0. pci operation in maint state when the pcm state machine is in the maint state, the pci state machine does not control the above functions. in this state all the data paths are under the control of software. software controls the data paths via several control bits in the plc_cntrl_a register. software can also override the pci functions when the pcm state machine is not in the maint state by setting the config_cntrl bit in the plc_cntrl_b register. pci state machine the function of the pci state machine is described in table 14 and figure 3. table 14. pci state description state description pci0 in this state the pci causes plc-s to be (removed) bypassed. a transition is made to insert_scrub when set_sc_join signal is asserted. a transition is made to inserted if class_s or pcm_maint is set. pci1 in this state scrubbing is performed. (insert scrub) a transition is made to inserted after t_scrub length of time. pci2 in this state scrubbing is performed. (remove scrub) a transition is made to removed (or to inserted if class_s is set) after t_scrub length of time. pci3 in this state scrubbing has completed and (inserted) the data paths exists between the pdt/pdr and the mac. a transition is made to the remove_scrub state if the start_ scrubbing signal is asserted. a transition is made to the insert_scrub state if the set_sc_join signal is asserted (will only occur if class_s is set). note: user cannot disable pci.
amd p r e l i m i n a r y 3-39 AM79C864A removed pci0 insert scrub pci1 inserted pci3 remove scrub pci2 5 4 3 2 7 1 6 notes: 1. class = s or pcm_maint 2. not (sc_ join and not start_scrubbing) 3. set_sc_ join 4. tpc > t_scrub and (sc_join and not start_scrubbing) 5. set_sc_ join 6. not set_sc_join and start_scrubbing 7. tpc > t_scrub 15535b-15 reset signals on pci state machine: sc_join: this signal is output by the pcm state machine and indi- cates that is has reached the active state and scrubbing may be started. set_sc_join: this signal is output by the pcm state machine and is as- serted during the clock cycle before sc_join is asserted. class_s: this bit in the plc_cntrl_b register, when set, indicates that the station is of type class_s. start_scrubbing: this signal is asserted by the pcm state machine when the station has joined the ring (sc_join is asserted) and a break condition occurs. it causes the pci state machine to enter the remove_scrub state. pcm_maint: this signal indicates that the pcm state machine is in the maint state. figure 3. pci state machine decoder the decoder performs the 4b/5b decoding of received data symbols. the five bits of data from the elasticity buffer are decoded into four bits of data and one control bit, with the high order bit being the control bit. the de- coded symbol pairs are then sent to the mac. although the decoder operates on symbol pairs, each symbol is decoded independently of the other. until the pcm has completed establishing a connection for the physical link, the phy_invalid symbol is output by the decoder. whether the output of the decoder or the data on tx 9C0 is output on rx 9C0 is dependent on the class_s bit in the plc_cntrl_b register. in ad- dition, a violation symbol (v) shall be generated when an input error condition has been detected, such as an elasticity buffer error (buffer overflow or underflow). phy_invalid takes precedence over violation, so if an elasticity buffer error occurs while the current line state is quiet, halt, master, or noise then phy_invalid (1f in hex) is given to mac. the symbol decoding is shown in table 15.
amd p r e l i m i n a r y 3-40 the supernet 2 family for fddi 1994 data book table 15. 4b/5b decoding of data symbol encoded input decoded output q 0 0 0 0 0 1 0 0 0 0 i 1 1 1 1 1 1 0 1 1 1 h 0 0 1 0 0 1 0 1 0 0 j 1 1 0 0 0 1 1 1 0 0 k 1 0 0 0 1 1 0 0 1 1 t 0 1 1 0 1 1 1 1 0 1 r 0 0 1 1 1 1 0 0 0 1 s 1 1 0 0 1 1 1 0 0 1 h 0 0 0 0 1 1 0 1 0 0 h 0 0 0 1 0 1 0 1 0 0 v 0 0 0 1 1 1 1 0 0 0 v 0 0 1 0 1 1 1 0 0 0 v 0 0 1 1 0 1 1 0 0 0 h 0 1 0 0 0 1 0 1 0 0 v 0 1 1 0 0 1 1 0 0 0 h 1 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 2 1 0 1 0 0 0 0 0 1 0 3 1 0 1 0 1 0 0 0 1 1 4 0 1 0 1 0 0 0 1 0 0 5 0 1 0 1 1 0 0 1 0 1 6 0 1 1 1 0 0 0 1 1 0 7 0 1 1 1 1 0 0 1 1 1 8 1 0 0 1 0 0 1 0 0 0 9 1 0 0 1 1 0 1 0 0 1 a 1 0 1 1 0 0 1 0 1 0 b 1 0 1 1 1 0 1 0 1 1 c 1 1 0 1 0 0 1 1 0 0 d 1 1 0 1 1 0 1 1 0 1 e 1 1 1 0 0 0 1 1 1 0 f 1 1 1 0 1 0 1 1 1 1 encoder the encoder performs the 4b/5b encoding of data sym- bols to be transmitted over the physical medium. the four bits of data and one control bit from the mac are encoded into a unique five bit symbol which is sent to the pdt. although the encoder operates on symbol pairs, each symbol is encoded independently of the other. the symbol encoding is defined in table 16. table 16. 4b/5b encoding of data symbol data input encoded output q 1 0 0 0 0 0 0 0 0 0 i 1 0 1 1 1 1 1 1 1 1 h 1 0 1 0 0 0 0 1 0 0 j 1 1 1 0 0 1 1 0 0 0 k 1 0 0 1 1 1 0 0 0 1 t 1 1 1 0 1 0 1 1 0 1 r 1 0 0 0 1 0 0 1 1 1 s 1 1 0 0 1 1 1 0 0 1 inv 1 1 1 1 0 1 1 1 1 1 inv 1 0 0 10 1 1 1 1 1 inv 1 0 1 0 1 1 1 1 1 1 inv 1 0 1 1 0 1 1 1 1 1 inv 1 1 1 1 1 1 1 1 1 1 inv 1 1 0 0 0 1 1 1 1 1 inv 1 1 0 1 0 1 1 1 1 1 inv 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 2 0 0 0 1 0 1 0 1 0 0 3 0 0 0 1 1 1 0 1 0 1 4 0 0 1 0 0 0 1 0 1 0 5 0 0 1 0 1 0 1 0 1 1 6 0 0 1 1 0 0 1 1 1 0 7 0 0 1 1 1 0 1 1 1 1 8 0 1 0 0 0 1 0 0 1 0 9 0 1 0 0 1 1 0 0 1 1 a 0 1 0 1 0 1 0 1 1 0 b 0 1 0 1 1 1 0 1 1 1 c 0 1 1 0 0 1 1 0 1 0 d 0 1 1 0 1 1 1 0 1 1 e 0 1 1 1 0 1 1 1 0 0 f 0 1 1 1 1 1 1 1 0 1 stream cipher scrambler background a popular implementation of fddi is the replacement of fiber with unshielded twisted pair wire (utp). when a digital signal is transmitted over copper wire it radiates radio frequency (rf) energy. fddi encoded data has re- petitive patterns which result in peaks in the rf spectrum
amd p r e l i m i n a r y 3-41 AM79C864A large enough to keep the system from being approved by regulatory agencies such as the fcc. the peaks in the radiated signal can be reduced signifi- cantly by scrambling the transmitted signal. scramblers add the output of a random generator to the data signal. the resulting signal has fewer repetitive data patterns. thus the occurrence and amplitude of peaks in the fre- quency spectrum, of the transmitted signal, are greatly reduced and the probability of a systems approval by regulatory agencies, such as the fcc, is increased. the scrambled data is descrambled, at the receiver, by adding it to the output of another random generator. the receivers random generator has the same function as the transmitters random generator. because the ran- dom generators are the same and anything exclusive- ored with itself is zero, the output of the descrambler is the original data signal. data ? a = s_data s_data ? b = d_data a = b therefore a ? b = 0 and data ? a ? b = d_data = data where data = original data s_data = scrambled data d_data = unscrambled data a = transmitter random generator b = receiver descrambler ? = exclusive-or function for proper operation, the random generator in the descrambler must be synchronized to the random gen- erator in the scrambler, i.e., the random generators must be in the same state with respect to the data. be- cause the random generators operate independently of each other, they require synchronizing circuitry. the descrambler synchronizes itself to the scrambler by utilizing the following relationship. h[n] = s_data[n] ? s_data[n-j] ? s_data[n-i] = data[n] where h[n] = a hypothesis bit j and i are bit delays this relationship is true when data[n-j] = data[n-k]. the requirements for a correct h(n) are approximated during the fddi line states ils, qls, hls and mls. when a line state is detected, the corresponding correct data can be deduced. the proper setting for the random generator can be derived from data and s_data. if a ? data = s_data then data ? s_data = a the x3t9 committee has chosen x 11 + x 9 as the random generator function. this can be represented as a shift register with the eleventh and ninth bits fed back to the input of the first bit via an exclusive or gate (figure 4). for this polynomial, j equals eleven and i equals nine. table 17 shows the line state bits and the corresponding h bits. table 17. line states line state data h qls 00000000000 00000000000 ils 11111111111 11111111111 hls 00100001000 01110011100 mls 00100000000 01110000000 the following rules apply to the descrambler. when a line state is not detected, the input to the random gen- erator is bit 11 exclusive-ored with bit 9. data is s_data exclusive-ored with the random generator out- put. when a line state is detected, data is derived from h in accordance with table 17. the input to the random generator is data exclusive ored with s_data. scrambler a functional diagram of the scrambler is shown in figure 4. it combines the output of a random generator (x 11 + x 9 ) with fddi-encoded data via an xor gate. descrambler the descrambler (figure 5) combines the output of a random generator with the scrambled data to produce an exact copy of the original unscrambled data. the ran- dom generator has the same function as the random generator in the scrambler (x 11 + x 9 ). the descrambler has a state-synchronizer to set the descrambler-random generator to the same state as the scrambler-random generator. the state-synchronizer is enabled by scrm_rsync, which is from the plc-s decoder. when scrm_rsync is true, the decoder has not detected a valid fddi signal. the state-syn- chronizer attempts to set the random generator. if scrm_rsync is false, the data is valid and the ran- dom generator is assumed to be synchronized to the scrambler and will remain synchronized. the state-synchronizer monitors the scrambled data for one of the patterns in table 17. when there is a match, the output data is set to the corresponding value. the random generators input is the deduced output xored with the scrambled data input, which corresponds to the scramblers random generator. when there is not a match, the output data is the scrambled data xored with the random generators output. the random gen- erator is open loop.
amd p r e l i m i n a r y 3-42 the supernet 2 family for fddi 1994 data book using the stream cipher scrambler the system has access to the scrambler and descrambler through a pin and a register. pin 41 (scrm) and bit 0 (cipher_enable) of plc_cntrl_c enable the scrambler. scrm and table 18. stream cipher enable scrm cipher enable scrambler low low disabled low high enabled high low enabled high high enabled cipher_enable are ored together so either one high overrides the other (table 18). pin 41 is a ground pin on previous versions of the plc; therefore if the plc-s is to be used in the fiber mode, it can be inserted in a previously manufactured board without any changes. 11109876543 21 s_data 15535b-16 data figure 4. stream cipher scrambler 5 5 5 5 5 5 5 5 + C + C scrm_rsync s_data data/d_data state synchronizer capture deduced line state random generator 15535b-17 figure 5. stream cipher descrambler repeat filter the main function of the repeat filter is to prevent the propagation of code violations and invalid line states from the inbound link to the outbound link. this function is not required if a mac layer is present in the station configuration (since mac will not propagate invalid line states and code violations). but certain station configu- rations consist of only phy layer entities (such as the path of the secondary ring inside a station with just one mac in the primary ring). in such cases, a phy layer implementation is expected to provide the repeat filter function. the repeat filter in the plc-s filters the symbol stream at the output of the remote loopback mux. invalid line states are not allowed to propagate through a station; they will be turned into an idle symbol stream. also, if the repeat filter detects a corrupted frame, it truncates the frame by transmitting four halt symbols and then idle symbols until a jk symbol pair is seen. the halt symbols will cause the next mac entity in the logical ring to count the frame as a lost frame. another function of the repeat filter is called the gobble_byte function. when the repeat filter
amd p r e l i m i n a r y 3-43 AM79C864A detects a fragment, i.e., a frame in which idle symbols appears before the ending delimiter, then it changes the previous symbol pair to idles. after passing through re- peat filters in other stations, the fragment will eventually be completely converted to idles. the plc-s includes the symbol pair wide implementa- tion of the repeat filter as defined in the fddi phy document. data stream generator the data stream generator block uses a multiplexer for the purpose of generating a symbol pair at the request of the pcm via an internal signal bus ls_req (or external through control when the pcm is in the maint state by using the maint_ls bits in the plc_cntrl_b regis- ter), the repeat filter via an internal signal rf-cntrl (1_0), or transmitting the symbol pair from tx 9C0. the data_strm(9C0) is an internal bus that comes from the data stream generator to the encoder block. the data stream generator also latches the data each bclk cycle. this is done for the gobble_byte func- tion of the repeat filter (see above) which requires that the data be delayed for one clock cycle. data path muxes the receive data path and transmit data path of the plc-s include six multiplexers (muxes) for the pur- pose of altering the normal flow of data through the chip (see chip block diagram). reasons for altering the data paths are for physical connection insertion and removal and for testing and diagnostics. all receive and transmit data paths internal to the plc-s are ten bits (two symbols) wide. eb local loopback mux in normal operating mode, the eb local loopback mux puts the data held in the receive data input latch to the input of framer. when the eb_loc_loop bit in the plc_cntrl_a register is set or when the built-in self test is running, the mux loops back the data in the transmit data output latch onto the receive data path just after the receive data input latch (i.e., to the input of framer). this cre- ates a path whereby data from a mac device can trav- erse the entire transmit and receive data paths of the plc-ss (excluding the scrambler and the descrambler) and be returned to the mac device. the built-in self test uses this loopback along with the remote loopback to create a loop which covers all of the transmit data path and receive data path. cipher loopback mux in normal operating mode, the cipher lookback mux puts the data from pdr to the input of the descrambler block of plc-ss and the data from the scrambler block of plc-ss to pdt. when the cipher_lpbck bit in the plc_cntrl_c register is set, the mux loops back the output of the descrambler to the input of the scrambler. this creates a path whereby data from a mac device can traverse the entire transmit and receive data paths of the plc-ss (including the scrambler and the descrambler) and be returned to the mac device. lm local loopback mux in normal operating mode, the lm local loopback mux puts the output of elasticity buffer/smoother block to the input of decoder block. when the lm_loc_loop bit in the plc_cntrl_a register is set or when the built-in self test is running, the mux loops back the data in the transmit data output latch onto the receive data path just after the elasticity buffer. this differs from the eb_loc_loop in that the framer and elasticity buffer are bypassed. bypass mux in normal operating mode, the bypass mux sends the data output by the decoder to the receive data output latch. when the sc_bypass bit in the plc_cntrl_a regis- ter is set while the pcm is in the maint state, or when the config_cntrl bit is set in the plc_cntrl_b register, or when the pci is in the removed, in- sert_scrub, or remove_scrub state, the output of the bypass mux is put to the transmit data input latch onto the receive data path. on reset this bypass_mux will be in effect and will put the transmit data input latch onto the receive data path. remote loopback mux in normal operating mode, the remote loopback mux puts the data held in the transmit data input latch onto the transmit data path of the plc-ss. when the sc_rem_loop bit is set (and eb_loc_loop, lm_loc_loop and cipher_ lpbck bits are not set) or when the bist is running, this mux loops back the data from the decoder onto the transmit data path and is latched at this point. this cre- ates a path whereby data from the pdr can traverse the entire receive and transmit data paths of the plc-s and be transmitted by pdt. bist uses this loopback along with the local loopback to create a loop which also cov- ers all of the receive data path and the transmit data path. scrub mux the scrub mux selects its input from either constant idle symbol pairs or the output of the bypass_mux. when the req_scrub bit in the plc_cntrl_a reg- ister is set while the pcm is in the maint state, or when config_cntrl bits is set in the plc_cntrl_b
amd p r e l i m i n a r y 3-44 the supernet 2 family for fddi 1994 data book register, the pci is in the insert_scrub or remove_scrub state, the output of the scrub mux is idle symbols. otherwise transmit data from the bypass_mux is placed on the receive data output latch. this mux is used when the plc-s operates in a con- centrator. when a port in a concentrator is connecting to an end station, idle symbols are output on rx 9C0 so as to scrub the ring before the station starts putting data onto the ring. when a port in a concentrator is not con- nected to another station, the port is bypassed by routing tx back out on rx. test data mux in normal operating mode the test data mux sends the data output by the encoder to the transmit data output latch. when the built-in self test is running the test data mux selects the input from the bist block. this is how bist inserts pseudo-random test data into the loop it forms with the transmit and receive data paths. this point was chosen to inject test data because it was desired to avoid sending the test data through the repeat filter and the data stream generator. since both of these logic blocks act as filters, coverage of stuck-at faults in other parts of the chip would be reduced if data from these blocks rather than random test data were used. data input/output the plc-s contains four ports for receiving and trans- mitting network data: receive data input, receive data output, transmit data input, and transmit data output. the signal timing for these ports is detailed in the switching characteristics and switching waveforms chapters of this document. receive data input rdat is a five-bit (symbol wide) data bus going from the pdr chip to the plc-s. rsclk is also input from the pdr chip and is divided by two to get a recovered byte clock. rdat is latched on each rising and falling edge of the recovered byte clock. following the rising edge of the recovered byte clock, the five bits (symbol) just latched, plus the five bits (symbol) latched by the previ- ous falling edge recovered byte clock edge, are used in- ternally in the plc-s. all data paths inside the plc-s are 10 bits (two symbols) wide. receive data output rx is a ten-bit (symbol pair wide) data bus going from the plc-s to the a mac device in a single attachment station (sas). in the case of a concentrator or a dual attachment station (das), rx may also go to another plc-s. data is latched inside the plc-s on each rising edge of bclk and is available to the mac device shortly after this clock edge. transmit data input tx is a ten-bit (symbol pair wide) data bus going from the mac device (or in a concentrator/das, from an- other plc to the plc-s. the data is latched by the fall- ing edge of lsclk that precedes the rising edge of bclk. then it is latched again by that rising edge of bclk. assuming no skew between lsclk and bclk, this effectively adds a one half lsclk period to the hold time provided on tx. any amount by which bclk trails lsclk will subtract from the hold time provided. transmit data output tdat is a five-bit (symbol wide) data bus going from the plc-s to the pdt. the ten bit wide internal data bus is latched initially by the plc-s by each rising edge of bclk. bits nine through five are sent on the rising edge of lsclk following the rising edge of bclk. bits four through zero are then sent on the rising edge of lsclk following the falling edge of bclk. data are available to the pdt shortly after each rising edge of lsclk. built in self test (bist) the built in self test block contains logic to run the plc-s built in self test and also contains control logic for the chips counter segmentation test mode and boundary scan test mode. bist operation the bulk of the plc-s data path and state machine logic is tested by bist. it remains passive during normal chip operation. under test mode, bist tests the chip, and re- turns a signature which verifies the functioning of the chips logic with a high degree of certainty. since bist sits right on the silicon with the rest of the chip, it has the advantage of the optimum observability location: inside the chip. bist tests the plc-s by circulating pseudo random data throughout the chip. the various subcircuits within the chip are observed as they respond to these data, and a signature based upon their behavior is generated. this signature may be checked against the known cor- rect signature, to verify the functioning of the chip. a sin- gle fault in the chip, as long as it is covered by bist, will cause a different signature to be generated. the majority of the logic blocks of the plc-s sit directly on the chips data path. these blocks are easily tested by placing pseudo random vectors, generated by the linear feedback shift register (lsfr), on the data paths, and observing the behavior of the blocks with the signature generator. with this method, data from lfsr are input by the transmit data output latch lines via the test data mux (see block diagram on page 2). the test data are looped back onto the receive data path via the eb local loop- back mux. the test data traverse the entire receive data
amd p r e l i m i n a r y 3-45 AM79C864A path and are fed back to the signature generator. the test data are input to the transmit data path via the re- mote loopback mux. the test data are fed back to the signature generator before the transmit data path be- cause the repeat filter, data stream generator, and encoder act as filters which would reduce the fault cov- erage provided by the test data. fault coverage is ob- tained for the repeat filter, data stream generator, and encoder by separate signals fed to the signature generator. the state machines, while somewhat attached to the data path, are more control oriented, and are not likely to respond well to random vectors on the data paths. the lem, lsm, pcm, pci, and rf state machines are tested using scan logic. under test mode, the state reg- isters of the state machines, and their control bits in the registers of the npi are linked together to form a scan chain. the output of the scan chain drives a bit in the signature generator. bist is activated with the assertion of the run-bist bit in the plc_cntrl_a register. upon activation, the data path, lfsr, and signature generator are initial- ized, and the latches in the scan chain are placed in scan mode. after initialization, the lfsr and signature generator are enabled, and the test proceeds. when bist has completed, the signature is frozen, and may be read through the node processor interface. end of test occurs when a value of zero is reached in the lfsr. using a 16 bit lfsr clocked by the 80 ns bclk it will take approximately 5.24 ms to circulate 65535 test patterns through the chip. an interrupt to the node proc- essor after run_bist has been asserted, signifies the completion of the plc-s self test. this interrupt is cleared by clearing the run_bist bit in the plc_cntrl_a register (not by reading the intr_event register). bist is aborted if the run_bist bit is cleared by writing a zero in the run_ bist bit in the plc_cntrl_a register before bist completes. counter segmentation test mode the counters (including all timers) in the plc-s are de- signed in such a way, that under counter segmentation test mode, they break apart into several 4 bit counters. for example, in counter segmentation test mode, a 16-bit counter becomes four 4-bit counters. these 4-bit counters in parallel, allow the counters to be tested in 2 4 = 16 cycles, as opposed to 2 16 = 65536 cycles for a 16-bit counter. since counter test requires the ability to control the bclk, this test is not intended for any board level tests or diagnostics. this is a factory test only. boundary scan test mode in boundary scan test mode, most of the chip input and output latches are linked together to form a scan chain. while this complements bist, which does not test these latches, the main purpose of this test mode is for board testing. in this mode the i/o latches of the various chips on the board are linked into a large scan chain. by serially shifting data into the scan chain (boundary scan serial test mode), then clocking the data in parallel (normal or boundary scan parallel test mode) and then serially shifting the data out, the i/o latches and inter- connections between the various chips can be tested. the order of pins in the scan chain is shown in table 19. the pin test 0 is the scan chain input and the pin scano is the scan chain output. the pins rst , lsclk, bclk, npclk, rsclk, rrsclk, ebferr, lpbck , scrm, sdo, lsr 2C0, ulsb, encoff, test 2C0, ptsto, npaddr 4C0, int , cs , and nprw are not in- cluded in the scan chain. note that only the output por- tion of the np 15C0 bus is in the scan chain. bclk is used for clocking. table 19. boundary scan chain order pin type rdat0 input to rdat4 input fotoff output tdat4 output to tdat0 output tx0 input to tx9 input txpar input rxpar output rx9 output to rx0 output np 15 output to np 0 output
amd p r e l i m i n a r y 3-46 the supernet 2 family for fddi 1994 data book absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature 0 c to 70 c . . . . . . . . . . . . . . . supply voltage referenced to v ss C0.3 v to +7 v . . dc voltage applied to any pin referenced to v ss C0.5 to v dd + 0.5 v . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges temperature (t a )0 c to +70 c . . . . . . . . . . . . . . supply voltage, v dd +5 v +/C 5% . . . . . . . . . . . . . dc characteristics over operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v dd + 0.5 v v ol output low voltage i ol = 4 ma 0.4 v v oh output high voltage i oh = C4 ma 2.4 v i oz output leakage current (note 1) 0.4 v < v out < v dd C10 10 m a i ix input leakage current (note 2) 0 v < v in < v dd C10 10 m a parameter symbol parameter description test conditions min max unit i dd power supply current (note 3) v cc = max 125 ma f(bclk, npclk) = 12.5 mhz f(lsclk, rsclk) = 25 mhz notes: 1. i oz applies to all three-state output pins and bidirectional pins. 2. i ix applies to all input-only pins. 3. v il = 0.0 v and v ih = 3.0 v for i dd test. capacitance (see note 4) parameter symbol parameter description test conditions min max unit c in input pins 10 pf c i/o bidirectional pins (note 5) 10 pf notes: 4. pin capacitance is characterized at a frequency of 1 mhz, but is not 100% tested. 5. bidirectional and output pins are designed to drive a 50 pf capacitive load.
amd p r e l i m i n a r y 3-47 AM79C864A switching characteristics over commercial operating ranges parameter symbol parameter description min max unit 1 bclk period 80 ns 2 bclk pulse width low 38 42 ns 3 bclk pulse width high 38 42 ns 4 npclk period 80 ns 5 npclk pulse width low 38 42 ns 6 npclk pulse width high 38 42 ns 7 lsclk period 40 ns 8 lsclk pulse width low 15 ns 9 lsclk pulse width high 15 ns 10 rsclk period 40 ns 11 rsclk pulse width low 15 ns 12 rsclk pulse width high 10 ns 13 lsclk to bclk skew 2 8 ns 14 cs setup time 10 ns 15 cs hold time 10 ns 16 nprw, npaddr setup time 5 ns 17 nprw, npaddr hold time 20 ns 18 np driven to high impedence 30 ns 19 np driven 2 ns 20 np valid 30 ns 21 np invalid 2 ns 22 np setup time 30 ns 23 np hold time 20 ns 24 int asserted 40 ns 25 int deasserted 40 ns 26 rx, rxpar valid 25 ns 27 rx, rxpar invalid 3 ns 28 tx, txpar setup time 10 ns 29 tx, txpar hold time 5 ns 30 rdat setup time 5 ns 31 rdat hold time 8 ns 32 lprck fotoff , scan0, lsr, 25 ns ulsb, ebferr valid 33 lrrck , fotoff, scan0, lsr 2 ns ulsb, ebffrr invalid 34 sdo setup time 5 ns 35 sdo hold time 15 ns 36 tdat valid 25 ns 37 tdat invalid 3 ns 38 test 2-0 setup time 15 ns 39 test 2-0 hold time 15 ns 40 encoff setup time 15 ns 41 encoff hold time 10 ns 42 rst pulse width 20 bclk periods ns
amd p r e l i m i n a r y 3-48 the supernet 2 family for fddi 1994 data book key to switching waveforms ks000010 must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching waveforms bclk 15535bC18 132 npclk 13 lsclk 8 7 9 rsclk 10 11 12 4 65 plc-s clock timing parameters
amd p r e l i m i n a r y 3-49 AM79C864A switching waveforms 1 32 bclk 33 lpbck fotoff , scano lsr, ulsb, ebferr sdo 32 34 35 40 38 39 test2-0 41 encoff 15535b-19 plc-s misc signals timing diagram
amd p r e l i m i n a r y 3-50 the supernet 2 family for fddi 1994 data book switching waveforms 16 16 15535b-20 18 19 20 21 18 npclk cs nprw npaddr np int 14 14 15 15 17 17 16 17 16 17 22 23 18 24 25 4 5 6 node processor interface timing diagram 42 rst 15535b-21 plc-s reset timing parameters
amd p r e l i m i n a r y 3-51 AM79C864A switching waveforms 8 10 15535b-22 1 32 bclk rsclk 11 12 rdat 30 31 27 rx rxpar 26 7 9 lsclk 28 29 tx txpar 36 37 tdat plc-s data interface timing diagram
amd p r e l i m i n a r y 3-52 the supernet 2 family for fddi 1994 data book switching test circuit c l 0 v v t i ol i oh from output under test note: c l = 50 pf for all bidirectional or output pins. 15535b-23 standard test load
amd p r e l i m i n a r y 3-53 AM79C864A switching test waveforms input bus in high- impedance state 0.0 v 1.5 v 1.5 v input bus valid 3.0 v 15535b-24 1.5 v input waveform test points output bus valid output bus in high- impedance state enabled 1.5 v 1.5 v 15535b-25 output waveform test points

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